These changes introduces models for the PCIe Host Bridge (PHB4) of the POWER9 processor. It includes the PowerBus logic interface (PBCQ), IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI and LSI interrupt sources as found on a POWER9 system using the XIVE interrupt controller. POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and each PEC can have several PHBs. By default, * PEC0 provides 1 PHB (PHB0) * PEC1 provides 2 PHBs (PHB1 and PHB2) * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5) Each PEC has a set "global" registers and some "per-stack" (per-PHB) registers. Those are organized in two XSCOM ranges, the "Nest" range and the "PCI" range, each range contains both some "PEC" registers and some "per-stack" registers. No default device layout is provided and PCI devices can be added on any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip) with address 0x0 as the firwware (skiboot) only accepts a single device per root port. To run a simple system with a network and a storage adapters, use a command line options such as : -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0 -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0 -device megasas,id=scsi0,bus=pcie.1,addr=0x0 -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2 If more are needed, include a bridge. Multi chip is supported, each chip adding its set of PHB4 controllers and its PCI busses. The model doesn't emulate the EEH error handling. This model is not ready for hotplug yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [ clg: - numerous cleanups - commit log - fix for broken LSI support - PHB pic printinfo - large QOM rework ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144506.11132-2-clg@kaod.org> [dwg: Use device_class_set_props()] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
231 lines
6.2 KiB
C
231 lines
6.2 KiB
C
/*
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* QEMU PowerPC PowerNV (POWER9) PHB4 model
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*
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* Copyright (c) 2018-2020, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PCI_HOST_PNV_PHB4_H
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#define PCI_HOST_PNV_PHB4_H
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/ppc/xive.h"
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typedef struct PnvPhb4PecState PnvPhb4PecState;
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typedef struct PnvPhb4PecStack PnvPhb4PecStack;
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typedef struct PnvPHB4 PnvPHB4;
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typedef struct PnvChip PnvChip;
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/*
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* We have one such address space wrapper per possible device under
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* the PHB since they need to be assigned statically at qemu device
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* creation time. The relationship to a PE is done later
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* dynamically. This means we can potentially create a lot of these
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* guys. Q35 stores them as some kind of radix tree but we never
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* really need to do fast lookups so instead we simply keep a QLIST of
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* them for now, we can add the radix if needed later on.
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*
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* We do cache the PE number to speed things up a bit though.
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*/
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typedef struct PnvPhb4DMASpace {
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PCIBus *bus;
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uint8_t devfn;
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int pe_num; /* Cached PE number */
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#define PHB_INVALID_PE (-1)
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PnvPHB4 *phb;
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AddressSpace dma_as;
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IOMMUMemoryRegion dma_mr;
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MemoryRegion msi32_mr;
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MemoryRegion msi64_mr;
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QLIST_ENTRY(PnvPhb4DMASpace) list;
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} PnvPhb4DMASpace;
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/*
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* PHB4 PCIe Root port
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*/
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#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root-bus"
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#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
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typedef struct PnvPHB4RootPort {
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PCIESlot parent_obj;
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} PnvPHB4RootPort;
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/*
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* PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
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*/
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#define TYPE_PNV_PHB4 "pnv-phb4"
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#define PNV_PHB4(obj) OBJECT_CHECK(PnvPHB4, (obj), TYPE_PNV_PHB4)
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#define PNV_PHB4_MAX_LSIs 8
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#define PNV_PHB4_MAX_INTs 4096
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#define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2)
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#define PNV_PHB4_MAX_MMIO_WINDOWS 32
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#define PNV_PHB4_MIN_MMIO_WINDOWS 16
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#define PNV_PHB4_NUM_REGS (0x3000 >> 3)
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#define PNV_PHB4_MAX_PEs 512
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#define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2)
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#define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64)
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#define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2)
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#define PNV_PHB4_VERSION 0x000000a400000002ull
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#define PNV_PHB4_DEVICE_ID 0x04c1
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#define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
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struct PnvPHB4 {
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PCIExpressHost parent_obj;
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PnvPHB4RootPort root;
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uint32_t chip_id;
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uint32_t phb_id;
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uint64_t version;
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uint16_t device_id;
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char bus_path[8];
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/* Main register images */
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uint64_t regs[PNV_PHB4_NUM_REGS];
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MemoryRegion mr_regs;
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/* Extra SCOM-only register */
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uint64_t scom_hv_ind_addr_reg;
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/*
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* Geometry of the PHB. There are two types, small and big PHBs, a
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* number of resources (number of PEs, windows etc...) are doubled
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* for a big PHB
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*/
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bool big_phb;
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/* Memory regions for MMIO space */
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MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS];
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/* PCI side space */
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MemoryRegion pci_mmio;
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MemoryRegion pci_io;
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/* On-chip IODA tables */
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uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs];
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uint64_t ioda_MIST[PNV_PHB4_MAX_MIST];
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uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs];
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uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs];
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uint64_t ioda_MDT[PNV_PHB4_MAX_PEs];
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uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs];
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/*
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* The internal PESTA/B is 2 bits per PE split into two tables, we
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* store them in a single array here to avoid wasting space.
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*/
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uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs];
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/* P9 Interrupt generation */
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XiveSource xsrc;
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qemu_irq *qirqs;
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PnvPhb4PecStack *stack;
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QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces;
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};
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void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
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void pnv_phb4_update_regions(PnvPhb4PecStack *stack);
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extern const MemoryRegionOps pnv_phb4_xscom_ops;
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/*
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* PHB4 PEC (PCI Express Controller)
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*/
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#define TYPE_PNV_PHB4_PEC "pnv-phb4-pec"
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#define PNV_PHB4_PEC(obj) \
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OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB4_PEC)
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#define TYPE_PNV_PHB4_PEC_STACK "pnv-phb4-pec-stack"
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#define PNV_PHB4_PEC_STACK(obj) \
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OBJECT_CHECK(PnvPhb4PecStack, (obj), TYPE_PNV_PHB4_PEC_STACK)
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/* Per-stack data */
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struct PnvPhb4PecStack {
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DeviceState parent;
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/* My own stack number */
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uint32_t stack_no;
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/* Nest registers */
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#define PHB4_PEC_NEST_STK_REGS_COUNT 0x17
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uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT];
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MemoryRegion nest_regs_mr;
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/* PCI registers (excluding pass-through) */
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#define PHB4_PEC_PCI_STK_REGS_COUNT 0xf
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uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT];
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MemoryRegion pci_regs_mr;
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/* PHB pass-through XSCOM */
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MemoryRegion phb_regs_mr;
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/* Memory windows from PowerBus to PHB */
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MemoryRegion mmbar0;
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MemoryRegion mmbar1;
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MemoryRegion phbbar;
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MemoryRegion intbar;
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uint64_t mmio0_base;
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uint64_t mmio0_size;
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uint64_t mmio1_base;
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uint64_t mmio1_size;
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/* The owner PEC */
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PnvPhb4PecState *pec;
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/* The actual PHB */
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PnvPHB4 phb;
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};
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struct PnvPhb4PecState {
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DeviceState parent;
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/* PEC number in chip */
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uint32_t index;
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uint32_t chip_id;
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MemoryRegion *system_memory;
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/* Nest registers, excuding per-stack */
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#define PHB4_PEC_NEST_REGS_COUNT 0xf
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uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT];
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MemoryRegion nest_regs_mr;
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/* PCI registers, excluding per-stack */
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#define PHB4_PEC_PCI_REGS_COUNT 0x2
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uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT];
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MemoryRegion pci_regs_mr;
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/* Stacks */
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#define PHB4_PEC_MAX_STACKS 3
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uint32_t num_stacks;
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PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS];
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};
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#define PNV_PHB4_PEC_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvPhb4PecClass, (klass), TYPE_PNV_PHB4_PEC)
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#define PNV_PHB4_PEC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvPhb4PecClass, (obj), TYPE_PNV_PHB4_PEC)
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typedef struct PnvPhb4PecClass {
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DeviceClass parent_class;
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uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec);
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uint32_t xscom_nest_size;
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uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec);
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uint32_t xscom_pci_size;
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const char *compat;
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int compat_size;
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const char *stk_compat;
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int stk_compat_size;
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} PnvPhb4PecClass;
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#endif /* PCI_HOST_PNV_PHB4_H */
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