Let's add a proxy for virtio-mem, make it a memory device, and pass-through the properties. Reviewed-by: Pankaj Gupta <pankaj.gupta.linux@gmail.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20200626072248.78761-12-david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
870 lines
27 KiB
C
870 lines
27 KiB
C
#ifndef QEMU_PCI_H
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#define QEMU_PCI_H
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#include "exec/memory.h"
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#include "sysemu/dma.h"
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/* PCI includes legacy ISA access. */
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#include "hw/isa/isa.h"
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#include "hw/pci/pcie.h"
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extern bool pci_available;
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/* PCI bus */
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
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#define PCI_BUS_MAX 256
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#define PCI_DEVFN_MAX 256
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#define PCI_SLOT_MAX 32
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#define PCI_FUNC_MAX 8
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/* Class, Vendor and Device IDs from Linux's pci_ids.h */
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#include "hw/pci/pci_ids.h"
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/* QEMU-specific Vendor and Device ID definitions */
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/* IBM (0x1014) */
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#define PCI_DEVICE_ID_IBM_440GX 0x027f
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#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
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/* Hitachi (0x1054) */
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#define PCI_VENDOR_ID_HITACHI 0x1054
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#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
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/* Apple (0x106b) */
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#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
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#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
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#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
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#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
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#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
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/* Realtek (0x10ec) */
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#define PCI_DEVICE_ID_REALTEK_8029 0x8029
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/* Xilinx (0x10ee) */
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#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
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/* Marvell (0x11ab) */
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#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
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/* QEMU/Bochs VGA (0x1234) */
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#define PCI_VENDOR_ID_QEMU 0x1234
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#define PCI_DEVICE_ID_QEMU_VGA 0x1111
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#define PCI_DEVICE_ID_QEMU_IPMI 0x1112
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/* VMWare (0x15ad) */
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#define PCI_VENDOR_ID_VMWARE 0x15ad
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#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
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#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
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#define PCI_DEVICE_ID_VMWARE_NET 0x0720
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#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
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#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
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#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
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#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
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/* Intel (0x8086) */
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#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
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#define PCI_DEVICE_ID_INTEL_82557 0x1229
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#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
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/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBDEVICE_ID_QEMU 0x1100
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#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
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#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
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#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
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#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
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#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
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#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
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#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
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#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
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#define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
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#define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014
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#define PCI_DEVICE_ID_VIRTIO_MEM 0x1015
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#define PCI_VENDOR_ID_REDHAT 0x1b36
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#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
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#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
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#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
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#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
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#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
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#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
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#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
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#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
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#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
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#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
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#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
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#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
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#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
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#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
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#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
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#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
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#define FMT_PCIBUS PRIx64
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typedef uint64_t pcibus_t;
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struct PCIHostDeviceAddress {
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unsigned int domain;
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unsigned int bus;
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unsigned int slot;
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unsigned int function;
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};
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typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
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uint32_t address, uint32_t data, int len);
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typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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uint32_t address, int len);
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typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
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pcibus_t addr, pcibus_t size, int type);
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typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
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typedef struct PCIIORegion {
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pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
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#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
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pcibus_t size;
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uint8_t type;
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MemoryRegion *memory;
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MemoryRegion *address_space;
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} PCIIORegion;
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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enum {
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QEMU_PCI_VGA_MEM,
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QEMU_PCI_VGA_IO_LO,
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QEMU_PCI_VGA_IO_HI,
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QEMU_PCI_VGA_NUM_REGIONS,
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};
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#define QEMU_PCI_VGA_MEM_BASE 0xa0000
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#define QEMU_PCI_VGA_MEM_SIZE 0x20000
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#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
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#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
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#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
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#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
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#include "hw/pci/pci_regs.h"
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/* PCI HEADER_TYPE */
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#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
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/* Size of the standard PCI config header */
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#define PCI_CONFIG_HEADER_SIZE 0x40
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100
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/* Size of the standard PCIe config space: 4KB */
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#define PCIE_CONFIG_SPACE_SIZE 0x1000
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#define PCI_NUM_PINS 4 /* A-D */
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/* Bits in cap_present field. */
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enum {
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QEMU_PCI_CAP_MSI = 0x1,
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QEMU_PCI_CAP_MSIX = 0x2,
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QEMU_PCI_CAP_EXPRESS = 0x4,
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/* multifunction capable device */
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#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
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QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
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/* command register SERR bit enabled - unused since QEMU v5.0 */
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#define QEMU_PCI_CAP_SERR_BITNR 4
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QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
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/* Standard hot plug controller. */
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#define QEMU_PCI_SHPC_BITNR 5
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QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
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#define QEMU_PCI_SLOTID_BITNR 6
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QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
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/* PCI Express capability - Power Controller Present */
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#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
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QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
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/* Link active status in endpoint capability is always set */
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#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
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QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
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#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
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QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
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};
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#define TYPE_PCI_DEVICE "pci-device"
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#define PCI_DEVICE(obj) \
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OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
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#define PCI_DEVICE_CLASS(klass) \
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OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
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#define PCI_DEVICE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
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/* Implemented by devices that can be plugged on PCI Express buses */
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#define INTERFACE_PCIE_DEVICE "pci-express-device"
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/* Implemented by devices that can be plugged on Conventional PCI buses */
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#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
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typedef struct PCIINTxRoute {
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enum {
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PCI_INTX_ENABLED,
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PCI_INTX_INVERTED,
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PCI_INTX_DISABLED,
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} mode;
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int irq;
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} PCIINTxRoute;
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typedef struct PCIDeviceClass {
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DeviceClass parent_class;
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void (*realize)(PCIDevice *dev, Error **errp);
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PCIUnregisterFunc *exit;
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision;
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uint16_t class_id;
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uint16_t subsystem_vendor_id; /* only for header type = 0 */
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uint16_t subsystem_id; /* only for header type = 0 */
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/*
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* pci-to-pci bridge or normal device.
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* This doesn't mean pci host switch.
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* When card bus bridge is supported, this would be enhanced.
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*/
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bool is_bridge;
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/* rom bar */
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const char *romfile;
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} PCIDeviceClass;
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typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
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typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
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MSIMessage msg);
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typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
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typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
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unsigned int vector_start,
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unsigned int vector_end);
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enum PCIReqIDType {
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PCI_REQ_ID_INVALID = 0,
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PCI_REQ_ID_BDF,
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PCI_REQ_ID_SECONDARY_BUS,
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PCI_REQ_ID_MAX,
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};
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typedef enum PCIReqIDType PCIReqIDType;
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struct PCIReqIDCache {
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PCIDevice *dev;
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PCIReqIDType type;
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};
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typedef struct PCIReqIDCache PCIReqIDCache;
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struct PCIDevice {
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DeviceState qdev;
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bool partially_hotplugged;
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/* PCI config space */
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uint8_t *config;
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/* Used to enable config checks on load. Note that writable bits are
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* never checked even if set in cmask. */
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uint8_t *cmask;
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/* Used to implement R/W bytes */
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uint8_t *wmask;
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/* Used to implement RW1C(Write 1 to Clear) bytes */
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uint8_t *w1cmask;
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/* Used to allocate config space for capabilities. */
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uint8_t *used;
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/* the following fields are read only */
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int32_t devfn;
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/* Cached device to fetch requester ID from, to avoid the PCI
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* tree walking every time we invoke PCI request (e.g.,
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* MSI). For conventional PCI root complex, this field is
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* meaningless. */
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PCIReqIDCache requester_id_cache;
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char name[64];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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AddressSpace bus_master_as;
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MemoryRegion bus_master_container_region;
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MemoryRegion bus_master_enable_region;
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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/* Legacy PCI VGA regions */
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MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
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bool has_vga;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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uint8_t irq_state;
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/* Capability bits */
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uint32_t cap_present;
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/* Offset of MSI-X capability in config space */
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uint8_t msix_cap;
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/* MSI-X entries */
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int msix_entries_nr;
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/* Space to store MSIX table & pending bit array */
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uint8_t *msix_table;
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uint8_t *msix_pba;
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/* MemoryRegion container for msix exclusive BAR setup */
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MemoryRegion msix_exclusive_bar;
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/* Memory Regions for MSIX table and pending bit entries. */
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MemoryRegion msix_table_mmio;
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MemoryRegion msix_pba_mmio;
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/* Reference-count for entries actually in use by driver. */
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unsigned *msix_entry_used;
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/* MSIX function mask set or MSIX disabled */
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bool msix_function_masked;
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/* Version id needed for VMState */
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int32_t version_id;
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/* Offset of MSI capability in config space */
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uint8_t msi_cap;
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/* PCI Express */
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PCIExpressDevice exp;
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/* SHPC */
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SHPCDevice *shpc;
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/* Location of option rom */
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char *romfile;
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bool has_rom;
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MemoryRegion rom;
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uint32_t rom_bar;
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/* INTx routing notifier */
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PCIINTxRoutingNotifier intx_routing_notifier;
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/* MSI-X notifiers */
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MSIVectorUseNotifier msix_vector_use_notifier;
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MSIVectorReleaseNotifier msix_vector_release_notifier;
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MSIVectorPollNotifier msix_vector_poll_notifier;
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/* ID of standby device in net_failover pair */
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char *failover_pair_id;
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};
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void pci_register_bar(PCIDevice *pci_dev, int region_num,
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uint8_t attr, MemoryRegion *memory);
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void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
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MemoryRegion *io_lo, MemoryRegion *io_hi);
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void pci_unregister_vga(PCIDevice *pci_dev);
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pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
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int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
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uint8_t offset, uint8_t size,
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Error **errp);
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void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len);
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len);
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void pci_device_save(PCIDevice *s, QEMUFile *f);
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int pci_device_load(PCIDevice *s, QEMUFile *f);
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MemoryRegion *pci_address_space(PCIDevice *dev);
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MemoryRegion *pci_address_space_io(PCIDevice *dev);
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/*
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* Should not normally be used by devices. For use by sPAPR target
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* where QEMU emulates firmware.
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*/
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int pci_bar(PCIDevice *d, int reg);
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typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
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typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
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typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
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#define TYPE_PCI_BUS "PCI"
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#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
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#define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
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#define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
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#define TYPE_PCIE_BUS "PCIE"
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bool pci_bus_is_express(PCIBus *bus);
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void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
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const char *name,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io,
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uint8_t devfn_min, const char *typename);
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PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io,
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uint8_t devfn_min, const char *typename);
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void pci_root_bus_cleanup(PCIBus *bus);
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq);
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void pci_bus_irqs_cleanup(PCIBus *bus);
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int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
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/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
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static inline int pci_swizzle(int slot, int pin)
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{
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return (slot + pin) % PCI_NUM_PINS;
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}
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int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
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PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque,
|
|
MemoryRegion *address_space_mem,
|
|
MemoryRegion *address_space_io,
|
|
uint8_t devfn_min, int nirq,
|
|
const char *typename);
|
|
void pci_unregister_root_bus(PCIBus *bus);
|
|
void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
|
|
PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
|
|
bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
|
|
void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
|
|
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
|
|
PCIINTxRoutingNotifier notifier);
|
|
void pci_device_reset(PCIDevice *dev);
|
|
|
|
PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
|
|
const char *default_model,
|
|
const char *default_devaddr);
|
|
|
|
PCIDevice *pci_vga_init(PCIBus *bus);
|
|
|
|
static inline PCIBus *pci_get_bus(const PCIDevice *dev)
|
|
{
|
|
return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
|
|
}
|
|
int pci_bus_num(PCIBus *s);
|
|
static inline int pci_dev_bus_num(const PCIDevice *dev)
|
|
{
|
|
return pci_bus_num(pci_get_bus(dev));
|
|
}
|
|
|
|
int pci_bus_numa_node(PCIBus *bus);
|
|
void pci_for_each_device(PCIBus *bus, int bus_num,
|
|
void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
|
|
void *opaque);
|
|
void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
|
|
void (*fn)(PCIBus *bus, PCIDevice *d,
|
|
void *opaque),
|
|
void *opaque);
|
|
void pci_for_each_bus_depth_first(PCIBus *bus,
|
|
void *(*begin)(PCIBus *bus, void *parent_state),
|
|
void (*end)(PCIBus *bus, void *state),
|
|
void *parent_state);
|
|
PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
|
|
|
|
/* Use this wrapper when specific scan order is not required. */
|
|
static inline
|
|
void pci_for_each_bus(PCIBus *bus,
|
|
void (*fn)(PCIBus *bus, void *opaque),
|
|
void *opaque)
|
|
{
|
|
pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
|
|
}
|
|
|
|
PCIBus *pci_device_root_bus(const PCIDevice *d);
|
|
const char *pci_root_bus_path(PCIDevice *dev);
|
|
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
|
int pci_qdev_find_device(const char *id, PCIDevice **pdev);
|
|
void pci_bus_get_w64_range(PCIBus *bus, Range *range);
|
|
|
|
void pci_device_deassert_intx(PCIDevice *dev);
|
|
|
|
typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
|
|
|
|
AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
|
|
void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
|
|
|
|
static inline void
|
|
pci_set_byte(uint8_t *config, uint8_t val)
|
|
{
|
|
*config = val;
|
|
}
|
|
|
|
static inline uint8_t
|
|
pci_get_byte(const uint8_t *config)
|
|
{
|
|
return *config;
|
|
}
|
|
|
|
static inline void
|
|
pci_set_word(uint8_t *config, uint16_t val)
|
|
{
|
|
stw_le_p(config, val);
|
|
}
|
|
|
|
static inline uint16_t
|
|
pci_get_word(const uint8_t *config)
|
|
{
|
|
return lduw_le_p(config);
|
|
}
|
|
|
|
static inline void
|
|
pci_set_long(uint8_t *config, uint32_t val)
|
|
{
|
|
stl_le_p(config, val);
|
|
}
|
|
|
|
static inline uint32_t
|
|
pci_get_long(const uint8_t *config)
|
|
{
|
|
return ldl_le_p(config);
|
|
}
|
|
|
|
/*
|
|
* PCI capabilities and/or their fields
|
|
* are generally DWORD aligned only so
|
|
* mechanism used by pci_set/get_quad()
|
|
* must be tolerant to unaligned pointers
|
|
*
|
|
*/
|
|
static inline void
|
|
pci_set_quad(uint8_t *config, uint64_t val)
|
|
{
|
|
stq_le_p(config, val);
|
|
}
|
|
|
|
static inline uint64_t
|
|
pci_get_quad(const uint8_t *config)
|
|
{
|
|
return ldq_le_p(config);
|
|
}
|
|
|
|
static inline void
|
|
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
|
|
{
|
|
pci_set_word(&pci_config[PCI_VENDOR_ID], val);
|
|
}
|
|
|
|
static inline void
|
|
pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
|
|
{
|
|
pci_set_word(&pci_config[PCI_DEVICE_ID], val);
|
|
}
|
|
|
|
static inline void
|
|
pci_config_set_revision(uint8_t *pci_config, uint8_t val)
|
|
{
|
|
pci_set_byte(&pci_config[PCI_REVISION_ID], val);
|
|
}
|
|
|
|
static inline void
|
|
pci_config_set_class(uint8_t *pci_config, uint16_t val)
|
|
{
|
|
pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
|
|
}
|
|
|
|
static inline void
|
|
pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
|
|
{
|
|
pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
|
|
}
|
|
|
|
static inline void
|
|
pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
|
|
{
|
|
pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
|
|
}
|
|
|
|
/*
|
|
* helper functions to do bit mask operation on configuration space.
|
|
* Just to set bit, use test-and-set and discard returned value.
|
|
* Just to clear bit, use test-and-clear and discard returned value.
|
|
* NOTE: They aren't atomic.
|
|
*/
|
|
static inline uint8_t
|
|
pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
|
|
{
|
|
uint8_t val = pci_get_byte(config);
|
|
pci_set_byte(config, val & ~mask);
|
|
return val & mask;
|
|
}
|
|
|
|
static inline uint8_t
|
|
pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
|
|
{
|
|
uint8_t val = pci_get_byte(config);
|
|
pci_set_byte(config, val | mask);
|
|
return val & mask;
|
|
}
|
|
|
|
static inline uint16_t
|
|
pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
|
|
{
|
|
uint16_t val = pci_get_word(config);
|
|
pci_set_word(config, val & ~mask);
|
|
return val & mask;
|
|
}
|
|
|
|
static inline uint16_t
|
|
pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
|
|
{
|
|
uint16_t val = pci_get_word(config);
|
|
pci_set_word(config, val | mask);
|
|
return val & mask;
|
|
}
|
|
|
|
static inline uint32_t
|
|
pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
|
|
{
|
|
uint32_t val = pci_get_long(config);
|
|
pci_set_long(config, val & ~mask);
|
|
return val & mask;
|
|
}
|
|
|
|
static inline uint32_t
|
|
pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
|
|
{
|
|
uint32_t val = pci_get_long(config);
|
|
pci_set_long(config, val | mask);
|
|
return val & mask;
|
|
}
|
|
|
|
static inline uint64_t
|
|
pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
|
|
{
|
|
uint64_t val = pci_get_quad(config);
|
|
pci_set_quad(config, val & ~mask);
|
|
return val & mask;
|
|
}
|
|
|
|
static inline uint64_t
|
|
pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
|
|
{
|
|
uint64_t val = pci_get_quad(config);
|
|
pci_set_quad(config, val | mask);
|
|
return val & mask;
|
|
}
|
|
|
|
/* Access a register specified by a mask */
|
|
static inline void
|
|
pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
|
|
{
|
|
uint8_t val = pci_get_byte(config);
|
|
uint8_t rval = reg << ctz32(mask);
|
|
pci_set_byte(config, (~mask & val) | (mask & rval));
|
|
}
|
|
|
|
static inline uint8_t
|
|
pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
|
|
{
|
|
uint8_t val = pci_get_byte(config);
|
|
return (val & mask) >> ctz32(mask);
|
|
}
|
|
|
|
static inline void
|
|
pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
|
|
{
|
|
uint16_t val = pci_get_word(config);
|
|
uint16_t rval = reg << ctz32(mask);
|
|
pci_set_word(config, (~mask & val) | (mask & rval));
|
|
}
|
|
|
|
static inline uint16_t
|
|
pci_get_word_by_mask(uint8_t *config, uint16_t mask)
|
|
{
|
|
uint16_t val = pci_get_word(config);
|
|
return (val & mask) >> ctz32(mask);
|
|
}
|
|
|
|
static inline void
|
|
pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
|
|
{
|
|
uint32_t val = pci_get_long(config);
|
|
uint32_t rval = reg << ctz32(mask);
|
|
pci_set_long(config, (~mask & val) | (mask & rval));
|
|
}
|
|
|
|
static inline uint32_t
|
|
pci_get_long_by_mask(uint8_t *config, uint32_t mask)
|
|
{
|
|
uint32_t val = pci_get_long(config);
|
|
return (val & mask) >> ctz32(mask);
|
|
}
|
|
|
|
static inline void
|
|
pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
|
|
{
|
|
uint64_t val = pci_get_quad(config);
|
|
uint64_t rval = reg << ctz32(mask);
|
|
pci_set_quad(config, (~mask & val) | (mask & rval));
|
|
}
|
|
|
|
static inline uint64_t
|
|
pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
|
|
{
|
|
uint64_t val = pci_get_quad(config);
|
|
return (val & mask) >> ctz32(mask);
|
|
}
|
|
|
|
PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
|
|
const char *name);
|
|
PCIDevice *pci_new(int devfn, const char *name);
|
|
bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
|
|
|
|
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
|
bool multifunction,
|
|
const char *name);
|
|
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
|
|
|
|
void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
|
|
|
|
qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
|
|
void pci_set_irq(PCIDevice *pci_dev, int level);
|
|
|
|
static inline void pci_irq_assert(PCIDevice *pci_dev)
|
|
{
|
|
pci_set_irq(pci_dev, 1);
|
|
}
|
|
|
|
static inline void pci_irq_deassert(PCIDevice *pci_dev)
|
|
{
|
|
pci_set_irq(pci_dev, 0);
|
|
}
|
|
|
|
/*
|
|
* FIXME: PCI does not work this way.
|
|
* All the callers to this method should be fixed.
|
|
*/
|
|
static inline void pci_irq_pulse(PCIDevice *pci_dev)
|
|
{
|
|
pci_irq_assert(pci_dev);
|
|
pci_irq_deassert(pci_dev);
|
|
}
|
|
|
|
static inline int pci_is_express(const PCIDevice *d)
|
|
{
|
|
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
|
}
|
|
|
|
static inline int pci_is_express_downstream_port(const PCIDevice *d)
|
|
{
|
|
uint8_t type;
|
|
|
|
if (!pci_is_express(d) || !d->exp.exp_cap) {
|
|
return 0;
|
|
}
|
|
|
|
type = pcie_cap_get_type(d);
|
|
|
|
return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
|
|
}
|
|
|
|
static inline uint32_t pci_config_size(const PCIDevice *d)
|
|
{
|
|
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
|
}
|
|
|
|
static inline uint16_t pci_get_bdf(PCIDevice *dev)
|
|
{
|
|
return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
|
|
}
|
|
|
|
uint16_t pci_requester_id(PCIDevice *dev);
|
|
|
|
/* DMA access functions */
|
|
static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
|
|
{
|
|
return &dev->bus_master_as;
|
|
}
|
|
|
|
static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
|
|
void *buf, dma_addr_t len, DMADirection dir)
|
|
{
|
|
dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
|
|
return 0;
|
|
}
|
|
|
|
static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
|
|
void *buf, dma_addr_t len)
|
|
{
|
|
return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
|
|
}
|
|
|
|
static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
|
|
const void *buf, dma_addr_t len)
|
|
{
|
|
return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
|
|
}
|
|
|
|
#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
|
|
static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
|
|
dma_addr_t addr) \
|
|
{ \
|
|
return ld##_l##_dma(pci_get_address_space(dev), addr); \
|
|
} \
|
|
static inline void st##_s##_pci_dma(PCIDevice *dev, \
|
|
dma_addr_t addr, uint##_bits##_t val) \
|
|
{ \
|
|
st##_s##_dma(pci_get_address_space(dev), addr, val); \
|
|
}
|
|
|
|
PCI_DMA_DEFINE_LDST(ub, b, 8);
|
|
PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
|
|
PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
|
|
PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
|
|
PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
|
|
PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
|
|
PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
|
|
|
|
#undef PCI_DMA_DEFINE_LDST
|
|
|
|
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
|
|
dma_addr_t *plen, DMADirection dir)
|
|
{
|
|
void *buf;
|
|
|
|
buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
|
|
return buf;
|
|
}
|
|
|
|
static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
|
|
DMADirection dir, dma_addr_t access_len)
|
|
{
|
|
dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
|
|
}
|
|
|
|
static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
|
|
int alloc_hint)
|
|
{
|
|
qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
|
|
}
|
|
|
|
extern const VMStateDescription vmstate_pci_device;
|
|
|
|
#define VMSTATE_PCI_DEVICE(_field, _state) { \
|
|
.name = (stringify(_field)), \
|
|
.size = sizeof(PCIDevice), \
|
|
.vmsd = &vmstate_pci_device, \
|
|
.flags = VMS_STRUCT, \
|
|
.offset = vmstate_offset_value(_state, _field, PCIDevice), \
|
|
}
|
|
|
|
#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
|
|
.name = (stringify(_field)), \
|
|
.size = sizeof(PCIDevice), \
|
|
.vmsd = &vmstate_pci_device, \
|
|
.flags = VMS_STRUCT|VMS_POINTER, \
|
|
.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
|
|
}
|
|
|
|
MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
|
|
|
|
#endif
|