Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020, and create a configurable property for each defaulting to 96 and 64 (respectively) so that device modelers can set the value appropriately for their SoC. Other ARM processors also set their maximum number of used IRQs appropriately. Set the maximum theoretical number of GIC interrupts to 1020 and update the save/restore code to only use the appropriate number for each SoC. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Andreas Färber <afaerber@suse.de> [Peter Maydell: fixed minor whitespace snafu] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
240 lines
7.3 KiB
C
240 lines
7.3 KiB
C
/*
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* ARM11MPCore internal peripheral emulation.
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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#include "qemu-timer.h"
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#define NCPU 4
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static inline int
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gic_get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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#include "arm_gic.c"
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/* MPCore private memory region. */
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typedef struct mpcore_priv_state {
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gic_state gic;
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uint32_t scu_control;
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int iomemtype;
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uint32_t old_timer_status[8];
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uint32_t num_cpu;
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qemu_irq *timer_irq;
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MemoryRegion iomem;
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MemoryRegion container;
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DeviceState *mptimer;
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uint32_t num_irq;
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} mpcore_priv_state;
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/* Per-CPU private memory mapped IO. */
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static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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int id;
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offset &= 0xff;
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/* SCU */
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switch (offset) {
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case 0x00: /* Control. */
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return s->scu_control;
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case 0x04: /* Configuration. */
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id = ((1 << s->num_cpu) - 1) << 4;
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return id | (s->num_cpu - 1);
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case 0x08: /* CPU status. */
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return 0;
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case 0x0c: /* Invalidate all. */
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return 0;
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default:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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}
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}
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static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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offset &= 0xff;
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/* SCU */
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switch (offset) {
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case 0: /* Control register. */
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s->scu_control = value & 1;
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break;
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case 0x0c: /* Invalidate all. */
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/* This is a no-op as cache is not emulated. */
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break;
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default:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps mpcore_scu_ops = {
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.read = mpcore_scu_read,
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.write = mpcore_scu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void mpcore_timer_irq_handler(void *opaque, int irq, int level)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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if (level && !s->old_timer_status[irq]) {
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gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1));
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}
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s->old_timer_status[irq] = level;
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}
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static void mpcore_priv_map_setup(mpcore_priv_state *s)
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{
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int i;
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SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
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memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
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memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
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memory_region_add_subregion(&s->container, 0, &s->iomem);
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/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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* at 0x200, 0x300...
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*/
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for (i = 0; i < (s->num_cpu + 1); i++) {
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target_phys_addr_t offset = 0x100 + (i * 0x100);
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memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]);
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}
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/* Add the regions for timer and watchdog for "current CPU" and
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* for each specific CPU.
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*/
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s->timer_irq = qemu_allocate_irqs(mpcore_timer_irq_handler,
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s, (s->num_cpu + 1) * 2);
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for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
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/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
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target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
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memory_region_add_subregion(&s->container, offset,
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sysbus_mmio_get_region(busdev, i));
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}
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memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
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/* Wire up the interrupt from each watchdog and timer. */
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for (i = 0; i < s->num_cpu * 2; i++) {
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sysbus_connect_irq(busdev, i, s->timer_irq[i]);
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}
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}
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static int mpcore_priv_init(SysBusDevice *dev)
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{
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mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
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gic_init(&s->gic, s->num_cpu, s->num_irq);
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s->mptimer = qdev_create(NULL, "arm_mptimer");
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qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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qdev_init_nofail(s->mptimer);
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mpcore_priv_map_setup(s);
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sysbus_init_mmio(dev, &s->container);
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return 0;
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}
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/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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controllers. The output of these, plus some of the raw input lines
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are fed into a single SMP-aware interrupt controller on the CPU. */
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typedef struct {
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SysBusDevice busdev;
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SysBusDevice *priv;
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qemu_irq cpuic[32];
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qemu_irq rvic[4][64];
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uint32_t num_cpu;
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} mpcore_rirq_state;
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/* Map baseboard IRQs onto CPU IRQ lines. */
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static const int mpcore_irq_map[32] = {
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-1, -1, -1, -1, 1, 2, -1, -1,
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-1, -1, 6, -1, 4, 5, -1, -1,
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-1, 14, 15, 0, 7, 8, -1, -1,
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-1, -1, -1, -1, 9, 3, -1, -1,
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};
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static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
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{
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mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
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int i;
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for (i = 0; i < 4; i++) {
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qemu_set_irq(s->rvic[i][irq], level);
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}
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if (irq < 32) {
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irq = mpcore_irq_map[irq];
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if (irq >= 0) {
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qemu_set_irq(s->cpuic[irq], level);
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}
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}
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}
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static int realview_mpcore_init(SysBusDevice *dev)
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{
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mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
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DeviceState *gic;
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DeviceState *priv;
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int n;
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int i;
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priv = qdev_create(NULL, "arm11mpcore_priv");
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qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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qdev_init_nofail(priv);
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s->priv = sysbus_from_qdev(priv);
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sysbus_pass_irq(dev, s->priv);
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for (i = 0; i < 32; i++) {
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s->cpuic[i] = qdev_get_gpio_in(priv, i);
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}
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/* ??? IRQ routing is hardcoded to "normal" mode. */
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for (n = 0; n < 4; n++) {
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gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
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s->cpuic[10 + n]);
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for (i = 0; i < 64; i++) {
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s->rvic[n][i] = qdev_get_gpio_in(gic, i);
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}
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}
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qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
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sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0));
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return 0;
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}
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static SysBusDeviceInfo mpcore_rirq_info = {
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.init = realview_mpcore_init,
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.qdev.name = "realview_mpcore",
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.qdev.size = sizeof(mpcore_rirq_state),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static SysBusDeviceInfo mpcore_priv_info = {
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.init = mpcore_priv_init,
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.qdev.name = "arm11mpcore_priv",
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.qdev.size = sizeof(mpcore_priv_state),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
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/* The ARM11 MPCORE TRM says the on-chip controller may have
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* anything from 0 to 224 external interrupt IRQ lines (with another
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* 32 internal). We default to 32+32, which is the number provided by
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* the ARM11 MPCore test chip in the Realview Versatile Express
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* coretile. Other boards may differ and should set this property
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* appropriately. Some Linux kernels may not boot if the hardware
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* has more IRQ lines than the kernel expects.
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*/
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DEFINE_PROP_UINT32("num-irq", mpcore_priv_state, num_irq, 64),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void arm11mpcore_register_devices(void)
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{
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sysbus_register_withprop(&mpcore_rirq_info);
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sysbus_register_withprop(&mpcore_priv_info);
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}
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device_init(arm11mpcore_register_devices)
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