The license information in this file is rather confusing. The text declares LGPL first, but then says that contributions after Jan 2012 are licensed under the GPL instead. How should the average user who just downloaded the release tarball know which part is now GPL and which is LGPL? Also, as far as I can see, the file has been added to QEMU *after* January in 2012, so the whole file should be GPL by default instead. Furthermore, looking at the text of the LGPL (see COPYING.LIB in the top directory), the license clearly states in section "3." that one should rather replace the license information in such a case instead. Thus let's clean up the confusing statements and use the proper GPL text only. Message-Id: <1549471435-21887-1-git-send-email-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
154 lines
4.5 KiB
C
154 lines
4.5 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/i2c/pm_smbus.h"
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#include "hw/pci/pci.h"
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#include "sysemu/sysemu.h"
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#include "hw/i386/ich9.h"
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#define ICH9_SMB_DEVICE(obj) \
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OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
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typedef struct ICH9SMBState {
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PCIDevice dev;
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bool irq_enabled;
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PMSMBus smb;
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} ICH9SMBState;
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static bool ich9_vmstate_need_smbus(void *opaque, int version_id)
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{
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return pm_smbus_vmstate_needed();
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}
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static const VMStateDescription vmstate_ich9_smbus = {
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.name = "ich9_smb",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, ICH9SMBState),
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VMSTATE_BOOL_TEST(irq_enabled, ICH9SMBState, ich9_vmstate_need_smbus),
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VMSTATE_STRUCT_TEST(smb, ICH9SMBState, ich9_vmstate_need_smbus, 1,
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pmsmb_vmstate, PMSMBus),
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VMSTATE_END_OF_LIST()
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}
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};
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static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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ICH9SMBState *s = ICH9_SMB_DEVICE(d);
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pci_default_write_config(d, address, val, len);
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if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
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uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
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if (hostc & ICH9_SMB_HOSTC_HST_EN) {
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memory_region_set_enabled(&s->smb.io, true);
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} else {
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memory_region_set_enabled(&s->smb.io, false);
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}
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s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
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if (hostc & ICH9_SMB_HOSTC_SSRESET) {
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s->smb.reset(&s->smb);
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s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
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}
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}
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}
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static void ich9_smbus_realize(PCIDevice *d, Error **errp)
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{
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ICH9SMBState *s = ICH9_SMB_DEVICE(d);
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/* TODO? D31IP.SMIP in chipset configuration space */
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pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
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pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
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/* TODO bar0, bar1: 64bit BAR support*/
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pm_smbus_init(&d->qdev, &s->smb, false);
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pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
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&s->smb.io);
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}
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static void ich9_smb_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
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k->revision = ICH9_A2_SMB_REVISION;
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k->class_id = PCI_CLASS_SERIAL_SMBUS;
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dc->vmsd = &vmstate_ich9_smbus;
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dc->desc = "ICH9 SMBUS Bridge";
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k->realize = ich9_smbus_realize;
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k->config_write = ich9_smbus_write_config;
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/*
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* Reason: part of ICH9 southbridge, needs to be wired up by
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* pc_q35_init()
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*/
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dc->user_creatable = false;
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}
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static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
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{
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ICH9SMBState *s = pmsmb->opaque;
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if (enabled == s->irq_enabled) {
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return;
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}
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s->irq_enabled = enabled;
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pci_set_irq(&s->dev, enabled);
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}
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I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
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{
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PCIDevice *d =
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pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
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ICH9SMBState *s = ICH9_SMB_DEVICE(d);
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s->smb.set_irq = ich9_smb_set_irq;
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s->smb.opaque = s;
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return s->smb.smbus;
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}
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static const TypeInfo ich9_smb_info = {
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.name = TYPE_ICH9_SMB_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(ICH9SMBState),
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.class_init = ich9_smb_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void ich9_smb_register(void)
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{
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type_register_static(&ich9_smb_info);
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}
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type_init(ich9_smb_register);
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