a44e82db0c
Increase the number of Microblaze registers QEMU will report when talking to GDB. Signed-off-by: Joe Komlodi <komlodi@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <1589393329-223076-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* MicroBlaze gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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/*
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* GDB expects registers to be reported in this order:
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* R0-R31
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* PC-BTR
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* PVR0-PVR11
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* EDR-TLBHI
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* SLR-SHR
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*/
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if (n < 32) {
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return gdb_get_reg32(mem_buf, env->regs[n]);
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} else {
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n -= 32;
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switch (n) {
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case 0 ... 5:
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return gdb_get_reg32(mem_buf, env->sregs[n]);
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/* PVR12 is intentionally skipped */
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case 6 ... 17:
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n -= 6;
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return gdb_get_reg32(mem_buf, env->pvr.regs[n]);
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case 18 ... 24:
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/* Add an offset of 6 to resume where we left off with SRegs */
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n = n - 18 + 6;
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return gdb_get_reg32(mem_buf, env->sregs[n]);
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case 25:
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return gdb_get_reg32(mem_buf, env->slr);
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case 26:
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return gdb_get_reg32(mem_buf, env->shr);
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default:
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return 0;
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}
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}
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}
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int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUMBState *env = &cpu->env;
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uint32_t tmp;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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tmp = ldl_p(mem_buf);
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if (n < 32) {
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env->regs[n] = tmp;
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} else {
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n -= 32;
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switch (n) {
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case 0 ... 5:
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env->sregs[n] = tmp;
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break;
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/* PVR12 is intentionally skipped */
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case 6 ... 17:
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n -= 6;
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env->pvr.regs[n] = tmp;
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break;
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case 18 ... 24:
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/* Add an offset of 6 to resume where we left off with SRegs */
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n = n - 18 + 6;
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env->sregs[n] = tmp;
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break;
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case 25:
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env->slr = tmp;
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break;
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case 26:
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env->shr = tmp;
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break;
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}
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}
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return 4;
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}
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