The v7M systick timer can be programmed to run from either of two clocks: * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0) * the main CPU clock (when SYST_CSR.CLKSOURCE == 1) Our implementation currently hardwires the external reference clock to be 1MHz, and allows boards to set the main CPU clock frequency via the global 'system_clock_scale'. (Most boards set that to a constant value; the Stellaris boards allow the guest to reprogram it via the board-specific RCC registers). As the first step in converting this to use the Clock infrastructure, add input clocks to the systick device for the reference clock and the CPU clock. The device implementation ignores them; once we have made all the users of the device correctly wire up the new Clocks we will switch the implementation to use them and ignore the old system_clock_scale. This is a migration compat break for all M-profile boards, because of the addition of the new clock objects to the vmstate struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-6-peter.maydell@linaro.org
257 lines
7.4 KiB
C
257 lines
7.4 KiB
C
/*
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* ARMv7M SysTick timer
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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* Copyright (c) 2017 Linaro Ltd
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* Written by Peter Maydell
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*
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* This code is licensed under the GPL (version 2 or later).
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*/
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#include "qemu/osdep.h"
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#include "hw/timer/armv7m_systick.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-clock.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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/* qemu timers run at 1GHz. We want something closer to 1MHz. */
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#define SYSTICK_SCALE 1000ULL
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#define SYSTICK_ENABLE (1 << 0)
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#define SYSTICK_TICKINT (1 << 1)
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#define SYSTICK_CLKSOURCE (1 << 2)
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#define SYSTICK_COUNTFLAG (1 << 16)
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int system_clock_scale;
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/* Conversion factor from qemu timer to SysTick frequencies. */
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static inline int64_t systick_scale(SysTickState *s)
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{
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if (s->control & SYSTICK_CLKSOURCE) {
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return system_clock_scale;
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} else {
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return 1000;
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}
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}
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static void systick_timer_tick(void *opaque)
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{
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SysTickState *s = (SysTickState *)opaque;
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trace_systick_timer_tick();
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s->control |= SYSTICK_COUNTFLAG;
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if (s->control & SYSTICK_TICKINT) {
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/* Tell the NVIC to pend the SysTick exception */
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qemu_irq_pulse(s->irq);
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}
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if (ptimer_get_limit(s->ptimer) == 0) {
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/*
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* Timer expiry with SYST_RVR zero disables the timer
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* (but doesn't clear SYST_CSR.ENABLE)
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*/
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ptimer_stop(s->ptimer);
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}
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}
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static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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SysTickState *s = opaque;
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uint32_t val;
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if (attrs.user) {
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/* Generate BusFault for unprivileged accesses */
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return MEMTX_ERROR;
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}
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switch (addr) {
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case 0x0: /* SysTick Control and Status. */
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val = s->control;
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s->control &= ~SYSTICK_COUNTFLAG;
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break;
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case 0x4: /* SysTick Reload Value. */
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val = ptimer_get_limit(s->ptimer);
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break;
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case 0x8: /* SysTick Current Value. */
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val = ptimer_get_count(s->ptimer);
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break;
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case 0xc: /* SysTick Calibration Value. */
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val = 10000;
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break;
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default:
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val = 0;
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qemu_log_mask(LOG_GUEST_ERROR,
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"SysTick: Bad read offset 0x%" HWADDR_PRIx "\n", addr);
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break;
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}
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trace_systick_read(addr, val, size);
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*data = val;
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return MEMTX_OK;
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}
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static MemTxResult systick_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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SysTickState *s = opaque;
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if (attrs.user) {
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/* Generate BusFault for unprivileged accesses */
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return MEMTX_ERROR;
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}
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trace_systick_write(addr, value, size);
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switch (addr) {
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case 0x0: /* SysTick Control and Status. */
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{
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uint32_t oldval;
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ptimer_transaction_begin(s->ptimer);
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oldval = s->control;
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s->control &= 0xfffffff8;
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s->control |= value & 7;
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if ((oldval ^ value) & SYSTICK_ENABLE) {
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if (value & SYSTICK_ENABLE) {
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/*
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* Always reload the period in case board code has
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* changed system_clock_scale. If we ever replace that
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* global with a more sensible API then we might be able
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* to set the period only when it actually changes.
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*/
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ptimer_set_period(s->ptimer, systick_scale(s));
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ptimer_run(s->ptimer, 0);
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} else {
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ptimer_stop(s->ptimer);
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}
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} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
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ptimer_set_period(s->ptimer, systick_scale(s));
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}
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ptimer_transaction_commit(s->ptimer);
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break;
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}
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case 0x4: /* SysTick Reload Value. */
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ptimer_transaction_begin(s->ptimer);
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ptimer_set_limit(s->ptimer, value & 0xffffff, 0);
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ptimer_transaction_commit(s->ptimer);
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break;
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case 0x8: /* SysTick Current Value. */
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/*
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* Writing any value clears SYST_CVR to zero and clears
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* SYST_CSR.COUNTFLAG. The counter will then reload from SYST_RVR
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* on the next clock edge unless SYST_RVR is zero.
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*/
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ptimer_transaction_begin(s->ptimer);
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if (ptimer_get_limit(s->ptimer) == 0) {
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ptimer_stop(s->ptimer);
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}
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ptimer_set_count(s->ptimer, 0);
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s->control &= ~SYSTICK_COUNTFLAG;
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ptimer_transaction_commit(s->ptimer);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps systick_ops = {
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.read_with_attrs = systick_read,
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.write_with_attrs = systick_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void systick_reset(DeviceState *dev)
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{
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SysTickState *s = SYSTICK(dev);
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/*
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* Forgetting to set system_clock_scale is always a board code
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* bug. We can't check this earlier because for some boards
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* (like stellaris) it is not yet configured at the point where
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* the systick device is realized.
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*/
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assert(system_clock_scale != 0);
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ptimer_transaction_begin(s->ptimer);
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s->control = 0;
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ptimer_stop(s->ptimer);
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ptimer_set_count(s->ptimer, 0);
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ptimer_set_limit(s->ptimer, 0, 0);
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ptimer_set_period(s->ptimer, systick_scale(s));
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ptimer_transaction_commit(s->ptimer);
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}
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static void systick_instance_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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SysTickState *s = SYSTICK(obj);
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memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
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s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
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}
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static void systick_realize(DeviceState *dev, Error **errp)
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{
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SysTickState *s = SYSTICK(dev);
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s->ptimer = ptimer_init(systick_timer_tick, s,
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PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
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PTIMER_POLICY_NO_COUNTER_ROUND_DOWN |
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PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
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PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
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}
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static const VMStateDescription vmstate_systick = {
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.name = "armv7m_systick",
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_CLOCK(refclk, SysTickState),
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VMSTATE_CLOCK(cpuclk, SysTickState),
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VMSTATE_UINT32(control, SysTickState),
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VMSTATE_INT64(tick, SysTickState),
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VMSTATE_PTIMER(ptimer, SysTickState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void systick_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_systick;
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dc->reset = systick_reset;
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dc->realize = systick_realize;
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}
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static const TypeInfo armv7m_systick_info = {
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.name = TYPE_SYSTICK,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = systick_instance_init,
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.instance_size = sizeof(SysTickState),
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.class_init = systick_class_init,
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};
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static void armv7m_systick_register_types(void)
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{
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type_register_static(&armv7m_systick_info);
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}
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type_init(armv7m_systick_register_types)
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