a4e143ac5b
Convert the Neon 3-reg-same VADD and VSUB insns to decodetree. Note that we don't need the neon_3r_sizes[op] check here because all size values are OK for VADD and VSUB; we'll add this when we convert the first insn that has size restrictions. For this we need one of the GVecGen*Fn typedefs currently in translate-a64.h; move them all to translate.h as a block so they are visible to the 32-bit decoder. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200430181003.21682-15-peter.maydell@linaro.org
47 lines
1.8 KiB
Plaintext
47 lines
1.8 KiB
Plaintext
# AArch32 Neon data-processing instruction descriptions
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#
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# Copyright (c) 2020 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# VFP/Neon register fields; same as vfp.decode
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%vm_dp 5:1 0:4
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%vn_dp 7:1 16:4
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%vd_dp 22:1 12:4
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# Encodings for Neon data processing instructions where the T32 encoding
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# is a simple transformation of the A32 encoding.
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# More specifically, this file covers instructions where the A32 encoding is
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# 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# and the T32 encoding is
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# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# This file works on the A32 encoding only; calling code for T32 has to
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# transform the insn into the A32 version first.
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######################################################################
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# 3-reg-same grouping:
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# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
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######################################################################
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&3same vm vn vd q size
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@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
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VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
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VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
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