5c4cbcf26c
Previously the only PCI bus supported was the emulated PCI bus with fixed DMA window with start at 0 and size 1GB. As we are going to support PCI pass through which DMA window properties are set by the host kernel, we have to support DMA windows with parameters other than default. This patch adds: 1. DMA window properties to sPAPRPHBState: LIOBN (bus id), start, size of the window. 2. An additional function spapr_dma_dt() to populate DMA window properties in the device tree which simply accepts all the parameters and does not try to guess what kind of IOMMU is given to it. The original spapr_dma_dt() is renamed to spapr_tcet_dma_dt(). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
/*
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* QEMU SPAPR PCI BUS definitions
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*
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* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined(__HW_SPAPR_H__)
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#error Please include spapr.h before this file!
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#endif
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#if !defined(__HW_SPAPR_PCI_H__)
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#define __HW_SPAPR_PCI_H__
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#include "hw/pci.h"
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#include "hw/pci_host.h"
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#include "hw/xics.h"
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#define SPAPR_MSIX_MAX_DEVS 32
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typedef struct sPAPRPHBState {
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PCIHostState host_state;
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uint64_t buid;
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char *busname;
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char *dtbusname;
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MemoryRegion memspace, iospace;
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target_phys_addr_t mem_win_addr, mem_win_size, io_win_addr, io_win_size;
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target_phys_addr_t msi_win_addr;
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MemoryRegion memwindow, iowindow, msiwindow;
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uint32_t dma_liobn;
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uint64_t dma_window_start;
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uint64_t dma_window_size;
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DMAContext *dma;
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struct {
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uint32_t irq;
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} lsi_table[PCI_NUM_PINS];
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struct {
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uint32_t config_addr;
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uint32_t irq;
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int nvec;
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} msi_table[SPAPR_MSIX_MAX_DEVS];
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QLIST_ENTRY(sPAPRPHBState) list;
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} sPAPRPHBState;
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static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
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{
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return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
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}
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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void spapr_create_phb(sPAPREnvironment *spapr,
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const char *busname, uint64_t buid,
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uint64_t mem_win_addr, uint64_t mem_win_size,
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uint64_t io_win_addr, uint64_t msi_win_addr);
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int spapr_populate_pci_dt(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt);
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void spapr_pci_rtas_init(void);
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#endif /* __HW_SPAPR_PCI_H__ */
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