haraldwolff/qemu-patch-raspberry4
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Eduardo Habkost a9f27ea9ad i386: Clean up cache CPUID code 
Always initialize CPUCaches structs with cache information, even
if legacy_cache=true.  Use different CPUCaches struct for
CPUID[2], CPUID[4], and the AMD CPUID leaves.

This will simplify a lot the logic inside cpu_x86_cpuid().

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Message-Id: <1527176614-26271-2-git-send-email-babu.moger@amd.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-06-08 15:54:10 -03:00
..
alpha tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
arm target/arm: Add trailing '\n' to qemu_log() calls 2018-06-08 13:15:33 +01:00
cris tcg-next queue 2018-06-04 11:28:31 +01:00
hppa tcg-next queue 2018-06-04 11:28:31 +01:00
i386 i386: Clean up cache CPUID code 2018-06-08 15:54:10 -03:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: Add trailing '\n' to qemu_log() call 2018-06-08 13:15:33 +01:00
microblaze tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
mips tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
moxie tcg-next queue 2018-06-04 11:28:31 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc tcg-next queue 2018-06-04 11:28:31 +01:00
ppc tcg-next queue 2018-06-04 11:28:31 +01:00
riscv RISC-V: Add trailing '\n' to qemu_log() calls 2018-06-08 13:15:33 +01:00
s390x tcg-next queue 2018-06-04 11:28:31 +01:00
sh4 tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
sparc move more data to arch specific files 2018-06-05 10:38:33 +01:00
tilegx tcg-next queue 2018-06-04 11:28:31 +01:00
tricore tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
unicore32 tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
xtensa target/xtensa: Add trailing '\n' to qemu_log() calls 2018-06-08 13:15:33 +01:00