fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
32 lines
1 KiB
Plaintext
32 lines
1 KiB
Plaintext
Correctness issues:
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- some eflags manipulation incorrectly reset the bit 0x2.
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- SVM: test, cpu save/restore, SMM save/restore.
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- x86_64: lcall/ljmp intel/amd differences ?
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- better code fetch (different exception handling + CS.limit support)
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- user/kernel PUSHL/POPL in helper.c
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- add missing cpuid tests
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- return UD exception if LOCK prefix incorrectly used
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- test ldt limit < 7 ?
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- fix some 16 bit sp push/pop overflow (pusha/popa, lcall lret)
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- full support of segment limit/rights
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- full x87 exception support
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- improve x87 bit exactness (use bochs code ?)
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- DRx register support
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- CR0.AC emulation
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- SSE alignment checks
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Optimizations/Features:
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- add SVM nested paging support
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- add VMX support
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- add AVX support
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- add SSE5 support
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- fxsave/fxrstor AMD extensions
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- improve monitor/mwait support
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- faster EFLAGS update: consider SZAP, C, O can be updated separately
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with a bit field in CC_OP and more state variables.
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- evaluate x87 stack pointer statically
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- find a way to avoid translating several time the same TB if CR0.TS
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is set or not.
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