24c328521b
The NPC SPR is really only supposed to be used for FPGA debugging. It contains the same contents as PC, unless one plays games. Follow the or1ksim implementation in flushing delayed branch state when it is changed. The PPC SPR need not be updated every instruction, merely when we exit the TB or attempt to read its contents. Signed-off-by: Richard Henderson <rth@twiddle.net>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/*
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* OpenRISC interrupt helper routines
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Feng Gao <gf91597@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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void HELPER(rfe)(CPUOpenRISCState *env)
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{
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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#ifndef CONFIG_USER_ONLY
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int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
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(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
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#endif
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cpu->env.pc = cpu->env.epcr;
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cpu_set_sr(&cpu->env, cpu->env.esr);
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cpu->env.lock_addr = -1;
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#ifndef CONFIG_USER_ONLY
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if (cpu->env.sr & SR_DME) {
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cpu->env.tlb->cpu_openrisc_map_address_data =
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&cpu_openrisc_get_phys_data;
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} else {
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cpu->env.tlb->cpu_openrisc_map_address_data =
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&cpu_openrisc_get_phys_nommu;
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}
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if (cpu->env.sr & SR_IME) {
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cpu->env.tlb->cpu_openrisc_map_address_code =
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&cpu_openrisc_get_phys_code;
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} else {
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cpu->env.tlb->cpu_openrisc_map_address_code =
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&cpu_openrisc_get_phys_nommu;
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}
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if (need_flush_tlb) {
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tlb_flush(cs);
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}
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#endif
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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