299f7bec5a
The Linux fec driver needs at least basic phy support to probe and work. The current qemu mcf_fec emulation has no support for the reading or writing of the MDIO lines to access an attached phy. This code adds a very simple set of register results for a fixed phy setup - very similar to that used on an m5208evb board. This is enough to probe and identify an emulated attached phy. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435296436-12152-4-git-send-email-gerg@uclinux.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
77 lines
2.3 KiB
C
77 lines
2.3 KiB
C
/*
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* Common network MII address and register definitions.
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*
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* Allwinner EMAC register definitions from Linux kernel are:
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* Copyright 2012 Stefan Roese <sr@denx.de>
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* Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
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* Copyright 1997 Sten Wang
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MII_H
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#define MII_H
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/* PHY registers */
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#define MII_BMCR 0
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#define MII_BMSR 1
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#define MII_PHYID1 2
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#define MII_PHYID2 3
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#define MII_ANAR 4
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#define MII_ANLPAR 5
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#define MII_ANER 6
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#define MII_NSR 16
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#define MII_LBREMR 17
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#define MII_REC 18
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#define MII_SNRDR 19
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#define MII_TEST 25
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/* PHY registers fields */
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#define MII_BMCR_RESET (1 << 15)
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#define MII_BMCR_LOOPBACK (1 << 14)
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#define MII_BMCR_SPEED (1 << 13)
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#define MII_BMCR_AUTOEN (1 << 12)
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#define MII_BMCR_FD (1 << 8)
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#define MII_BMSR_100TX_FD (1 << 14)
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#define MII_BMSR_100TX_HD (1 << 13)
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#define MII_BMSR_10T_FD (1 << 12)
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#define MII_BMSR_10T_HD (1 << 11)
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#define MII_BMSR_MFPS (1 << 6)
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#define MII_BMSR_AN_COMP (1 << 5)
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#define MII_BMSR_AUTONEG (1 << 3)
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#define MII_BMSR_LINK_ST (1 << 2)
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#define MII_ANAR_TXFD (1 << 8)
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#define MII_ANAR_TX (1 << 7)
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#define MII_ANAR_10FD (1 << 6)
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#define MII_ANAR_10 (1 << 5)
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#define MII_ANAR_CSMACD (1 << 0)
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#define MII_ANLPAR_ACK (1 << 14)
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#define MII_ANLPAR_TXFD (1 << 8)
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#define MII_ANLPAR_TX (1 << 7)
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#define MII_ANLPAR_10FD (1 << 6)
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#define MII_ANLPAR_10 (1 << 5)
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#define MII_ANLPAR_CSMACD (1 << 0)
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/* List of vendor identifiers */
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/* RealTek 8201 */
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#define RTL8201CP_PHYID1 0x0000
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#define RTL8201CP_PHYID2 0x8201
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/* National Semiconductor DP83848 */
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#define DP83848_PHYID1 0x2000
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#define DP83848_PHYID2 0x5c90
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#endif /* MII_H */
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