qemu_hexdump()'s pointer to the buffer and length of the buffer are closely related arguments but are widely separated in the argument list order (also, the format of <stdio.h> function prototypes is usually to have the FILE* argument coming first). Reorder the arguments as "fp, prefix, buf, size" which is more logical. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20200822180950.1343963-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
652 lines
20 KiB
C
652 lines
20 KiB
C
/*
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* QEMU Freescale eTSEC Emulator
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*
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* Copyright (c) 2011-2013 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "net/checksum.h"
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#include "qemu/log.h"
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#include "etsec.h"
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#include "registers.h"
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/* #define ETSEC_RING_DEBUG */
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/* #define HEX_DUMP */
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/* #define DEBUG_BD */
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#ifdef ETSEC_RING_DEBUG
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static const int debug_etsec = 1;
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#else
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static const int debug_etsec;
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#endif
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#define RING_DEBUG(fmt, ...) do { \
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if (debug_etsec) { \
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qemu_log(fmt , ## __VA_ARGS__); \
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} \
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} while (0)
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#ifdef DEBUG_BD
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static void print_tx_bd_flags(uint16_t flags)
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{
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qemu_log(" Ready: %d\n", !!(flags & BD_TX_READY));
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qemu_log(" PAD/CRC: %d\n", !!(flags & BD_TX_PADCRC));
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qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP));
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qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT));
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qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST));
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qemu_log(" Tx CRC: %d\n", !!(flags & BD_TX_TC));
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qemu_log(" User-defined preamble / defer: %d\n",
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!!(flags & BD_TX_PREDEF));
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qemu_log(" Huge frame enable / Late collision: %d\n",
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!!(flags & BD_TX_HFELC));
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qemu_log(" Control frame / Retransmission Limit: %d\n",
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!!(flags & BD_TX_CFRL));
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qemu_log(" Retry count: %d\n",
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(flags >> BD_TX_RC_OFFSET) & BD_TX_RC_MASK);
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qemu_log(" Underrun / TCP/IP off-load enable: %d\n",
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!!(flags & BD_TX_TOEUN));
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qemu_log(" Truncation: %d\n", !!(flags & BD_TX_TR));
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}
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static void print_rx_bd_flags(uint16_t flags)
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{
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qemu_log(" Empty: %d\n", !!(flags & BD_RX_EMPTY));
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qemu_log(" Receive software ownership: %d\n", !!(flags & BD_RX_RO1));
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qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP));
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qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT));
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qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST));
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qemu_log(" First in frame: %d\n", !!(flags & BD_RX_FIRST));
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qemu_log(" Miss: %d\n", !!(flags & BD_RX_MISS));
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qemu_log(" Broadcast: %d\n", !!(flags & BD_RX_BROADCAST));
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qemu_log(" Multicast: %d\n", !!(flags & BD_RX_MULTICAST));
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qemu_log(" Rx frame length violation: %d\n", !!(flags & BD_RX_LG));
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qemu_log(" Rx non-octet aligned frame: %d\n", !!(flags & BD_RX_NO));
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qemu_log(" Short frame: %d\n", !!(flags & BD_RX_SH));
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qemu_log(" Rx CRC Error: %d\n", !!(flags & BD_RX_CR));
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qemu_log(" Overrun: %d\n", !!(flags & BD_RX_OV));
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qemu_log(" Truncation: %d\n", !!(flags & BD_RX_TR));
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}
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static void print_bd(eTSEC_rxtx_bd bd, int mode, uint32_t index)
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{
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qemu_log("eTSEC %s Data Buffer Descriptor (%u)\n",
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mode == eTSEC_TRANSMIT ? "Transmit" : "Receive",
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index);
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qemu_log(" Flags : 0x%04x\n", bd.flags);
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if (mode == eTSEC_TRANSMIT) {
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print_tx_bd_flags(bd.flags);
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} else {
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print_rx_bd_flags(bd.flags);
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}
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qemu_log(" Length : 0x%04x\n", bd.length);
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qemu_log(" Pointer : 0x%08x\n", bd.bufptr);
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}
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#endif /* DEBUG_BD */
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static void read_buffer_descriptor(eTSEC *etsec,
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hwaddr addr,
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eTSEC_rxtx_bd *bd)
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{
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assert(bd != NULL);
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RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
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cpu_physical_memory_read(addr,
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bd,
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sizeof(eTSEC_rxtx_bd));
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if (etsec->regs[DMACTRL].value & DMACTRL_LE) {
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bd->flags = lduw_le_p(&bd->flags);
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bd->length = lduw_le_p(&bd->length);
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bd->bufptr = ldl_le_p(&bd->bufptr);
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} else {
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bd->flags = lduw_be_p(&bd->flags);
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bd->length = lduw_be_p(&bd->length);
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bd->bufptr = ldl_be_p(&bd->bufptr);
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}
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}
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static void write_buffer_descriptor(eTSEC *etsec,
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hwaddr addr,
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eTSEC_rxtx_bd *bd)
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{
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assert(bd != NULL);
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if (etsec->regs[DMACTRL].value & DMACTRL_LE) {
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stw_le_p(&bd->flags, bd->flags);
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stw_le_p(&bd->length, bd->length);
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stl_le_p(&bd->bufptr, bd->bufptr);
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} else {
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stw_be_p(&bd->flags, bd->flags);
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stw_be_p(&bd->length, bd->length);
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stl_be_p(&bd->bufptr, bd->bufptr);
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}
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RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
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cpu_physical_memory_write(addr,
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bd,
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sizeof(eTSEC_rxtx_bd));
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}
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static void ievent_set(eTSEC *etsec,
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uint32_t flags)
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{
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etsec->regs[IEVENT].value |= flags;
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etsec_update_irq(etsec);
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}
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static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len)
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{
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int add = min_frame_len - etsec->tx_buffer_len;
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/* Padding */
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if (add > 0) {
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RING_DEBUG("pad:%u\n", add);
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etsec->tx_buffer = g_realloc(etsec->tx_buffer,
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etsec->tx_buffer_len + add);
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memset(etsec->tx_buffer + etsec->tx_buffer_len, 0x0, add);
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etsec->tx_buffer_len += add;
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}
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/* Never add CRC in QEMU */
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}
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static void process_tx_fcb(eTSEC *etsec)
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{
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uint8_t flags = (uint8_t)(*etsec->tx_buffer);
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/* L3 header offset from start of frame */
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uint8_t l3_header_offset = (uint8_t)*(etsec->tx_buffer + 3);
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/* L4 header offset from start of L3 header */
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uint8_t l4_header_offset = (uint8_t)*(etsec->tx_buffer + 2);
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/* L3 header */
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uint8_t *l3_header = etsec->tx_buffer + 8 + l3_header_offset;
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/* L4 header */
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uint8_t *l4_header = l3_header + l4_header_offset;
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/* if packet is IP4 and IP checksum is requested */
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if (flags & FCB_TX_IP && flags & FCB_TX_CIP) {
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/* do IP4 checksum (TODO This function does TCP/UDP checksum
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* but not sure if it also does IP4 checksum.) */
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net_checksum_calculate(etsec->tx_buffer + 8,
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etsec->tx_buffer_len - 8);
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}
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/* TODO Check the correct usage of the PHCS field of the FCB in case the NPH
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* flag is on */
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/* if packet is IP4 and TCP or UDP */
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if (flags & FCB_TX_IP && flags & FCB_TX_TUP) {
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/* if UDP */
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if (flags & FCB_TX_UDP) {
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/* if checksum is requested */
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if (flags & FCB_TX_CTU) {
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/* do UDP checksum */
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net_checksum_calculate(etsec->tx_buffer + 8,
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etsec->tx_buffer_len - 8);
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} else {
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/* set checksum field to 0 */
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l4_header[6] = 0;
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l4_header[7] = 0;
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}
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} else if (flags & FCB_TX_CTU) { /* if TCP and checksum is requested */
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/* do TCP checksum */
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net_checksum_calculate(etsec->tx_buffer + 8,
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etsec->tx_buffer_len - 8);
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}
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}
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}
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static void process_tx_bd(eTSEC *etsec,
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eTSEC_rxtx_bd *bd)
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{
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uint8_t *tmp_buff = NULL;
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hwaddr tbdbth = (hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32;
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if (bd->length == 0) {
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/* ERROR */
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return;
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}
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if (etsec->tx_buffer_len == 0) {
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/* It's the first BD */
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etsec->first_bd = *bd;
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}
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/* TODO: if TxBD[TOE/UN] skip the Tx Frame Control Block*/
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/* Load this Data Buffer */
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etsec->tx_buffer = g_realloc(etsec->tx_buffer,
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etsec->tx_buffer_len + bd->length);
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tmp_buff = etsec->tx_buffer + etsec->tx_buffer_len;
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cpu_physical_memory_read(bd->bufptr + tbdbth, tmp_buff, bd->length);
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/* Update buffer length */
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etsec->tx_buffer_len += bd->length;
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if (etsec->tx_buffer_len != 0 && (bd->flags & BD_LAST)) {
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if (etsec->regs[MACCFG1].value & MACCFG1_TX_EN) {
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/* MAC Transmit enabled */
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/* Process offload Tx FCB */
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if (etsec->first_bd.flags & BD_TX_TOEUN) {
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process_tx_fcb(etsec);
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}
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if (etsec->first_bd.flags & BD_TX_PADCRC
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|| etsec->regs[MACCFG2].value & MACCFG2_PADCRC) {
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/* Padding and CRC (Padding implies CRC) */
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tx_padding_and_crc(etsec, 64);
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} else if (etsec->first_bd.flags & BD_TX_TC
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|| etsec->regs[MACCFG2].value & MACCFG2_CRC_EN) {
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/* Only CRC */
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/* Never add CRC in QEMU */
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}
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#if defined(HEX_DUMP)
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qemu_log("eTSEC Send packet size:%d\n", etsec->tx_buffer_len);
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qemu_hexdump(stderr, "", etsec->tx_buffer, etsec->tx_buffer_len);
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#endif /* ETSEC_RING_DEBUG */
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if (etsec->first_bd.flags & BD_TX_TOEUN) {
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qemu_send_packet(qemu_get_queue(etsec->nic),
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etsec->tx_buffer + 8,
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etsec->tx_buffer_len - 8);
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} else {
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qemu_send_packet(qemu_get_queue(etsec->nic),
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etsec->tx_buffer,
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etsec->tx_buffer_len);
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}
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}
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etsec->tx_buffer_len = 0;
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if (bd->flags & BD_INTERRUPT) {
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ievent_set(etsec, IEVENT_TXF);
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}
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} else {
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if (bd->flags & BD_INTERRUPT) {
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ievent_set(etsec, IEVENT_TXB);
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}
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}
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/* Update DB flags */
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/* Clear Ready */
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bd->flags &= ~BD_TX_READY;
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/* Clear Defer */
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bd->flags &= ~BD_TX_PREDEF;
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/* Clear Late Collision */
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bd->flags &= ~BD_TX_HFELC;
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/* Clear Retransmission Limit */
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bd->flags &= ~BD_TX_CFRL;
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/* Clear Retry Count */
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bd->flags &= ~(BD_TX_RC_MASK << BD_TX_RC_OFFSET);
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/* Clear Underrun */
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bd->flags &= ~BD_TX_TOEUN;
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/* Clear Truncation */
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bd->flags &= ~BD_TX_TR;
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}
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void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr)
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{
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hwaddr ring_base = 0;
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hwaddr bd_addr = 0;
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eTSEC_rxtx_bd bd;
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uint16_t bd_flags;
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if (!(etsec->regs[MACCFG1].value & MACCFG1_TX_EN)) {
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RING_DEBUG("%s: MAC Transmit not enabled\n", __func__);
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return;
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}
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ring_base = (hwaddr)(etsec->regs[TBASEH].value & 0xF) << 32;
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ring_base += etsec->regs[TBASE0 + ring_nbr].value & ~0x7;
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bd_addr = etsec->regs[TBPTR0 + ring_nbr].value & ~0x7;
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do {
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read_buffer_descriptor(etsec, bd_addr, &bd);
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#ifdef DEBUG_BD
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print_bd(bd,
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eTSEC_TRANSMIT,
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(bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd));
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#endif /* DEBUG_BD */
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/* Save flags before BD update */
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bd_flags = bd.flags;
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if (!(bd_flags & BD_TX_READY)) {
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break;
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}
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process_tx_bd(etsec, &bd);
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/* Write back BD after update */
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write_buffer_descriptor(etsec, bd_addr, &bd);
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/* Wrap or next BD */
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if (bd_flags & BD_WRAP) {
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bd_addr = ring_base;
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} else {
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bd_addr += sizeof(eTSEC_rxtx_bd);
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}
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} while (TRUE);
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/* Save the Buffer Descriptor Pointers to last bd that was not
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* succesfully closed */
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etsec->regs[TBPTR0 + ring_nbr].value = bd_addr;
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/* Set transmit halt THLTx */
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etsec->regs[TSTAT].value |= 1 << (31 - ring_nbr);
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}
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static void fill_rx_bd(eTSEC *etsec,
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eTSEC_rxtx_bd *bd,
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const uint8_t **buf,
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size_t *size)
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{
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uint16_t to_write;
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hwaddr bufptr = bd->bufptr +
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((hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32);
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uint8_t padd[etsec->rx_padding];
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uint8_t rem;
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RING_DEBUG("eTSEC fill Rx buffer @ 0x%016" HWADDR_PRIx
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" size:%zu(padding + crc:%u) + fcb:%u\n",
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bufptr, *size, etsec->rx_padding, etsec->rx_fcb_size);
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bd->length = 0;
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/* This operation will only write FCB */
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if (etsec->rx_fcb_size != 0) {
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cpu_physical_memory_write(bufptr, etsec->rx_fcb, etsec->rx_fcb_size);
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bufptr += etsec->rx_fcb_size;
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bd->length += etsec->rx_fcb_size;
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etsec->rx_fcb_size = 0;
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}
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/* We remove padding from the computation of to_write because it is not
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* allocated in the buffer.
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*/
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to_write = MIN(*size - etsec->rx_padding,
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etsec->regs[MRBLR].value - etsec->rx_fcb_size);
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/* This operation can only write packet data and no padding */
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if (to_write > 0) {
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cpu_physical_memory_write(bufptr, *buf, to_write);
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*buf += to_write;
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bufptr += to_write;
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*size -= to_write;
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bd->flags &= ~BD_RX_EMPTY;
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bd->length += to_write;
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}
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if (*size == etsec->rx_padding) {
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/* The remaining bytes are only for padding which is not actually
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* allocated in the data buffer.
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*/
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rem = MIN(etsec->regs[MRBLR].value - bd->length, etsec->rx_padding);
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if (rem > 0) {
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memset(padd, 0x0, sizeof(padd));
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etsec->rx_padding -= rem;
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*size -= rem;
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bd->length += rem;
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cpu_physical_memory_write(bufptr, padd, rem);
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}
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}
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}
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static void rx_init_frame(eTSEC *etsec, const uint8_t *buf, size_t size)
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{
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uint32_t fcb_size = 0;
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uint8_t prsdep = (etsec->regs[RCTRL].value >> RCTRL_PRSDEP_OFFSET)
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& RCTRL_PRSDEP_MASK;
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if (prsdep != 0) {
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/* Prepend FCB (FCB size + RCTRL[PAL]) */
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fcb_size = 8 + ((etsec->regs[RCTRL].value >> 16) & 0x1F);
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etsec->rx_fcb_size = fcb_size;
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/* TODO: fill_FCB(etsec); */
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memset(etsec->rx_fcb, 0x0, sizeof(etsec->rx_fcb));
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} else {
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etsec->rx_fcb_size = 0;
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}
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g_free(etsec->rx_buffer);
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/* Do not copy the frame for now */
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etsec->rx_buffer = (uint8_t *)buf;
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etsec->rx_buffer_len = size;
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|
|
/* CRC padding (We don't have to compute the CRC) */
|
|
etsec->rx_padding = 4;
|
|
|
|
/*
|
|
* Ensure that payload length + CRC length is at least 802.3
|
|
* minimum MTU size bytes long (64)
|
|
*/
|
|
if (etsec->rx_buffer_len < 60) {
|
|
etsec->rx_padding += 60 - etsec->rx_buffer_len;
|
|
}
|
|
|
|
etsec->rx_first_in_frame = 1;
|
|
etsec->rx_remaining_data = etsec->rx_buffer_len;
|
|
RING_DEBUG("%s: rx_buffer_len:%u rx_padding+crc:%u\n", __func__,
|
|
etsec->rx_buffer_len, etsec->rx_padding);
|
|
}
|
|
|
|
ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size)
|
|
{
|
|
int ring_nbr = 0; /* Always use ring0 (no filer) */
|
|
|
|
if (etsec->rx_buffer_len != 0) {
|
|
RING_DEBUG("%s: We can't receive now,"
|
|
" a buffer is already in the pipe\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
if (etsec->regs[RSTAT].value & 1 << (23 - ring_nbr)) {
|
|
RING_DEBUG("%s: The ring is halted\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
if (etsec->regs[DMACTRL].value & DMACTRL_GRS) {
|
|
RING_DEBUG("%s: Graceful receive stop\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
if (!(etsec->regs[MACCFG1].value & MACCFG1_RX_EN)) {
|
|
RING_DEBUG("%s: MAC Receive not enabled\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
if ((etsec->regs[RCTRL].value & RCTRL_RSF) && (size < 60)) {
|
|
/* CRC is not in the packet yet, so short frame is below 60 bytes */
|
|
RING_DEBUG("%s: Drop short frame\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
rx_init_frame(etsec, buf, size);
|
|
|
|
etsec_walk_rx_ring(etsec, ring_nbr);
|
|
|
|
return size;
|
|
}
|
|
|
|
void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr)
|
|
{
|
|
hwaddr ring_base = 0;
|
|
hwaddr bd_addr = 0;
|
|
hwaddr start_bd_addr = 0;
|
|
eTSEC_rxtx_bd bd;
|
|
uint16_t bd_flags;
|
|
size_t remaining_data;
|
|
const uint8_t *buf;
|
|
uint8_t *tmp_buf;
|
|
size_t size;
|
|
|
|
if (etsec->rx_buffer_len == 0) {
|
|
/* No frame to send */
|
|
RING_DEBUG("No frame to send\n");
|
|
return;
|
|
}
|
|
|
|
remaining_data = etsec->rx_remaining_data + etsec->rx_padding;
|
|
buf = etsec->rx_buffer
|
|
+ (etsec->rx_buffer_len - etsec->rx_remaining_data);
|
|
size = etsec->rx_buffer_len + etsec->rx_padding;
|
|
|
|
ring_base = (hwaddr)(etsec->regs[RBASEH].value & 0xF) << 32;
|
|
ring_base += etsec->regs[RBASE0 + ring_nbr].value & ~0x7;
|
|
start_bd_addr = bd_addr = etsec->regs[RBPTR0 + ring_nbr].value & ~0x7;
|
|
|
|
do {
|
|
read_buffer_descriptor(etsec, bd_addr, &bd);
|
|
|
|
#ifdef DEBUG_BD
|
|
print_bd(bd,
|
|
eTSEC_RECEIVE,
|
|
(bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd));
|
|
|
|
#endif /* DEBUG_BD */
|
|
|
|
/* Save flags before BD update */
|
|
bd_flags = bd.flags;
|
|
|
|
if (bd_flags & BD_RX_EMPTY) {
|
|
fill_rx_bd(etsec, &bd, &buf, &remaining_data);
|
|
|
|
if (etsec->rx_first_in_frame) {
|
|
bd.flags |= BD_RX_FIRST;
|
|
etsec->rx_first_in_frame = 0;
|
|
etsec->rx_first_bd = bd;
|
|
}
|
|
|
|
/* Last in frame */
|
|
if (remaining_data == 0) {
|
|
|
|
/* Clear flags */
|
|
|
|
bd.flags &= ~0x7ff;
|
|
|
|
bd.flags |= BD_LAST;
|
|
|
|
/* NOTE: non-octet aligned frame is impossible in qemu */
|
|
|
|
if (size >= etsec->regs[MAXFRM].value) {
|
|
/* frame length violation */
|
|
qemu_log("%s frame length violation: size:%zu MAXFRM:%d\n",
|
|
__func__, size, etsec->regs[MAXFRM].value);
|
|
|
|
bd.flags |= BD_RX_LG;
|
|
}
|
|
|
|
if (size < 64) {
|
|
/* Short frame */
|
|
bd.flags |= BD_RX_SH;
|
|
}
|
|
|
|
/* TODO: Broadcast and Multicast */
|
|
|
|
if (bd.flags & BD_INTERRUPT) {
|
|
/* Set RXFx */
|
|
etsec->regs[RSTAT].value |= 1 << (7 - ring_nbr);
|
|
|
|
/* Set IEVENT */
|
|
ievent_set(etsec, IEVENT_RXF);
|
|
}
|
|
|
|
} else {
|
|
if (bd.flags & BD_INTERRUPT) {
|
|
/* Set IEVENT */
|
|
ievent_set(etsec, IEVENT_RXB);
|
|
}
|
|
}
|
|
|
|
/* Write back BD after update */
|
|
write_buffer_descriptor(etsec, bd_addr, &bd);
|
|
}
|
|
|
|
/* Wrap or next BD */
|
|
if (bd_flags & BD_WRAP) {
|
|
bd_addr = ring_base;
|
|
} else {
|
|
bd_addr += sizeof(eTSEC_rxtx_bd);
|
|
}
|
|
} while (remaining_data != 0
|
|
&& (bd_flags & BD_RX_EMPTY)
|
|
&& bd_addr != start_bd_addr);
|
|
|
|
/* Reset ring ptr */
|
|
etsec->regs[RBPTR0 + ring_nbr].value = bd_addr;
|
|
|
|
/* The frame is too large to fit in the Rx ring */
|
|
if (remaining_data > 0) {
|
|
|
|
/* Set RSTAT[QHLTx] */
|
|
etsec->regs[RSTAT].value |= 1 << (23 - ring_nbr);
|
|
|
|
/* Save remaining data to send the end of the frame when the ring will
|
|
* be restarted
|
|
*/
|
|
etsec->rx_remaining_data = remaining_data;
|
|
|
|
/* Copy the frame */
|
|
tmp_buf = g_malloc(size);
|
|
memcpy(tmp_buf, etsec->rx_buffer, size);
|
|
etsec->rx_buffer = tmp_buf;
|
|
|
|
RING_DEBUG("no empty RxBD available any more\n");
|
|
} else {
|
|
etsec->rx_buffer_len = 0;
|
|
etsec->rx_buffer = NULL;
|
|
if (etsec->need_flush) {
|
|
qemu_flush_queued_packets(qemu_get_queue(etsec->nic));
|
|
}
|
|
}
|
|
|
|
RING_DEBUG("eTSEC End of ring_write: remaining_data:%zu\n", remaining_data);
|
|
}
|