Georg Kotheimer ace544532c target/riscv: Fix update of hstatus.SPVP ... When trapping from virt into HS mode, hstatus.SPVP was set to the value of sstatus.SPP, as according to the specification both flags should be set to the same value. However, the assignment of SPVP takes place before SPP itself is updated, which results in SPVP having an outdated value. Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201013151054.396481-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-10-22 12:00:22 -07:00
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insn_trans	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu.c	target/riscv: Set instance_align on RISCVCPU TypeInfo	2020-09-18 13:59:51 -04:00
cpu.h	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	2020-09-18 14:12:32 -04:00
cpu_bits.h	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
cpu_helper.c	target/riscv: Fix update of hstatus.SPVP	2020-10-22 12:00:22 -07:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	icount: rename functions to be consistent with the module name	2020-10-05 16:41:22 +02:00
fpu_helper.c	target/riscv: Check nanboxed inputs to fp helpers	2020-08-21 22:37:55 -07:00
gdbstub.c	gdbstub: extend GByteArray to read register helpers	2020-03-17 17:38:38 +00:00
helper.h	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Check nanboxed inputs to fp helpers	2020-08-21 22:37:55 -07:00
meson.build	meson: target	2020-08-21 06:30:35 -04:00
monitor.c	target/riscv: Drop support for ISA spec version 1.09.1	2020-06-03 09:11:51 -07:00
op_helper.c	riscv: Convert interrupt logs to use qemu_log_mask()	2020-10-22 12:00:22 -07:00
pmp.c	target/riscv: Change the TLB page size depends on PMP entries.	2020-08-21 22:37:55 -07:00
pmp.h	target/riscv: Change the TLB page size depends on PMP entries.	2020-08-21 22:37:55 -07:00
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Update the Hypervisor trap return/entry	2020-08-25 09:11:36 -07:00
vector_helper.c	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00