This series removes ad hoc RAM allocation API (memory_region_allocate_system_memory) and consolidates it around hostmem backend. It allows to * resolve conflicts between global -mem-prealloc and hostmem's "policy" option, fixing premature allocation before binding policy is applied * simplify complicated memory allocation routines which had to deal with 2 ways to allocate RAM. * reuse hostmem backends of a choice for main RAM without adding extra CLI options to duplicate hostmem features. A recent case was -mem-shared, to enable vhost-user on targets that don't support hostmem backends [1] (ex: s390) * move RAM allocation from individual boards into generic machine code and provide them with prepared MemoryRegion. * clean up deprecated NUMA features which were tied to the old API (see patches) - "numa: remove deprecated -mem-path fallback to anonymous RAM" - (POSTPONED, waiting on libvirt side) "forbid '-numa node,mem' for 5.0 and newer machine types" - (POSTPONED) "numa: remove deprecated implicit RAM distribution between nodes" Introduce a new machine.memory-backend property and wrapper code that aliases global -mem-path and -mem-alloc into automatically created hostmem backend properties (provided memory-backend was not set explicitly given by user). A bulk of trivial patches then follow to incrementally convert individual boards to using machine.memory-backend provided MemoryRegion. Board conversion typically involves: * providing MachineClass::default_ram_size and MachineClass::default_ram_id so generic code could create default backend if user didn't explicitly provide memory-backend or -m options * dropping memory_region_allocate_system_memory() call * using convenience MachineState::ram MemoryRegion, which points to MemoryRegion allocated by ram-memdev On top of that for some boards: * missing ram_size checks are added (typically it were boards with fixed ram size) * ram_size fixups are replaced by checks and hard errors, forcing user to provide correct "-m" values instead of ignoring it and continuing running. After all boards are converted, the old API is removed and memory allocation routines are cleaned up.
985 lines
27 KiB
C
985 lines
27 KiB
C
/*
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* NeXT Cube System Driver
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*
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* Copyright (c) 2011 Bryce Lanham
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published
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* by the Free Software Foundation; either version 2 of the License,
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* or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/hwaddr.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "hw/irq.h"
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#include "hw/m68k/next-cube.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/scsi/esp.h"
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#include "hw/sysbus.h"
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#include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
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#include "hw/block/fdc.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "ui/console.h"
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#include "target/m68k/cpu.h"
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/* #define DEBUG_NEXT */
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#ifdef DEBUG_NEXT
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#define DPRINTF(fmt, ...) \
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do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do { } while (0)
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#endif
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#define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
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#define NEXT_MACHINE(obj) OBJECT_CHECK(NeXTState, (obj), TYPE_NEXT_MACHINE)
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#define ENTRY 0x0100001e
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#define RAM_SIZE 0x4000000
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#define ROM_FILE "Rev_2.5_v66.bin"
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typedef struct next_dma {
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uint32_t csr;
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uint32_t saved_next;
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uint32_t saved_limit;
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uint32_t saved_start;
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uint32_t saved_stop;
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uint32_t next;
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uint32_t limit;
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uint32_t start;
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uint32_t stop;
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uint32_t next_initbuf;
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uint32_t size;
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} next_dma;
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typedef struct NextRtc {
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uint8_t ram[32];
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uint8_t command;
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uint8_t value;
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uint8_t status;
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uint8_t control;
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uint8_t retval;
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} NextRtc;
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typedef struct {
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MachineState parent;
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uint32_t int_mask;
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uint32_t int_status;
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uint8_t scsi_csr_1;
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uint8_t scsi_csr_2;
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next_dma dma[10];
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qemu_irq *scsi_irq;
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qemu_irq scsi_dma;
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qemu_irq scsi_reset;
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qemu_irq *fd_irq;
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uint32_t scr1;
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uint32_t scr2;
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NextRtc rtc;
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} NeXTState;
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/* Thanks to NeXT forums for this */
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/*
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static const uint8_t rtc_ram3[32] = {
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0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
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0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
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};
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*/
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static const uint8_t rtc_ram2[32] = {
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0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
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0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
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};
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#define SCR2_RTCLK 0x2
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#define SCR2_RTDATA 0x4
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#define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
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static void nextscr2_write(NeXTState *s, uint32_t val, int size)
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{
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static int led;
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static int phase;
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static uint8_t old_scr2;
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uint8_t scr2_2;
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NextRtc *rtc = &s->rtc;
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if (size == 4) {
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scr2_2 = (val >> 8) & 0xFF;
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} else {
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scr2_2 = val & 0xFF;
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}
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if (val & 0x1) {
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DPRINTF("fault!\n");
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led++;
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if (led == 10) {
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DPRINTF("LED flashing, possible fault!\n");
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led = 0;
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}
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}
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if (scr2_2 & 0x1) {
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/* DPRINTF("RTC %x phase %i\n", scr2_2, phase); */
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if (phase == -1) {
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phase = 0;
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}
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/* If we are in going down clock... do something */
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if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) &&
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((scr2_2 & SCR2_RTCLK) == 0)) {
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if (phase < 8) {
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rtc->command = (rtc->command << 1) |
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((scr2_2 & SCR2_RTDATA) ? 1 : 0);
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}
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if (phase >= 8 && phase < 16) {
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rtc->value = (rtc->value << 1) |
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((scr2_2 & SCR2_RTDATA) ? 1 : 0);
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/* if we read RAM register, output RT_DATA bit */
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if (rtc->command <= 0x1F) {
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scr2_2 = scr2_2 & (~SCR2_RTDATA);
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if (rtc->ram[rtc->command] & (0x80 >> (phase - 8))) {
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scr2_2 |= SCR2_RTDATA;
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}
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rtc->retval = (rtc->retval << 1) |
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((scr2_2 & SCR2_RTDATA) ? 1 : 0);
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}
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/* read the status 0x30 */
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if (rtc->command == 0x30) {
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scr2_2 = scr2_2 & (~SCR2_RTDATA);
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/* for now status = 0x98 (new rtc + FTU) */
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if (rtc->status & (0x80 >> (phase - 8))) {
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scr2_2 |= SCR2_RTDATA;
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}
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rtc->retval = (rtc->retval << 1) |
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((scr2_2 & SCR2_RTDATA) ? 1 : 0);
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}
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/* read the status 0x31 */
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if (rtc->command == 0x31) {
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scr2_2 = scr2_2 & (~SCR2_RTDATA);
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if (rtc->control & (0x80 >> (phase - 8))) {
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scr2_2 |= SCR2_RTDATA;
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}
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rtc->retval = (rtc->retval << 1) |
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((scr2_2 & SCR2_RTDATA) ? 1 : 0);
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}
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if ((rtc->command >= 0x20) && (rtc->command <= 0x2F)) {
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scr2_2 = scr2_2 & (~SCR2_RTDATA);
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/* for now 0x00 */
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time_t time_h = time(NULL);
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struct tm *info = localtime(&time_h);
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int ret = 0;
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switch (rtc->command) {
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case 0x20:
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ret = SCR2_TOBCD(info->tm_sec);
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break;
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case 0x21:
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ret = SCR2_TOBCD(info->tm_min);
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break;
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case 0x22:
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ret = SCR2_TOBCD(info->tm_hour);
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break;
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case 0x24:
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ret = SCR2_TOBCD(info->tm_mday);
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break;
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case 0x25:
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ret = SCR2_TOBCD((info->tm_mon + 1));
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break;
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case 0x26:
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ret = SCR2_TOBCD((info->tm_year - 100));
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break;
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}
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if (ret & (0x80 >> (phase - 8))) {
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scr2_2 |= SCR2_RTDATA;
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}
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rtc->retval = (rtc->retval << 1) |
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((scr2_2 & SCR2_RTDATA) ? 1 : 0);
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}
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}
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phase++;
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if (phase == 16) {
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if (rtc->command >= 0x80 && rtc->command <= 0x9F) {
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rtc->ram[rtc->command - 0x80] = rtc->value;
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}
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/* write to x30 register */
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if (rtc->command == 0xB1) {
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/* clear FTU */
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if (rtc->value & 0x04) {
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rtc->status = rtc->status & (~0x18);
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s->int_status = s->int_status & (~0x04);
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}
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}
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}
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}
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} else {
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/* else end or abort */
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phase = -1;
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rtc->command = 0;
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rtc->value = 0;
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}
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s->scr2 = val & 0xFFFF00FF;
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s->scr2 |= scr2_2 << 8;
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old_scr2 = scr2_2;
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}
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static uint32_t mmio_readb(NeXTState *s, hwaddr addr)
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{
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switch (addr) {
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case 0xc000:
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return (s->scr1 >> 24) & 0xFF;
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case 0xc001:
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return (s->scr1 >> 16) & 0xFF;
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case 0xc002:
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return (s->scr1 >> 8) & 0xFF;
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case 0xc003:
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return (s->scr1 >> 0) & 0xFF;
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case 0xd000:
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return (s->scr2 >> 24) & 0xFF;
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case 0xd001:
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return (s->scr2 >> 16) & 0xFF;
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case 0xd002:
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return (s->scr2 >> 8) & 0xFF;
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case 0xd003:
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return (s->scr2 >> 0) & 0xFF;
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case 0x14020:
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DPRINTF("MMIO Read 0x4020\n");
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return 0x7f;
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default:
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DPRINTF("MMIO Read B @ %"HWADDR_PRIx"\n", addr);
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return 0x0;
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}
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}
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static uint32_t mmio_readw(NeXTState *s, hwaddr addr)
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{
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switch (addr) {
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default:
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DPRINTF("MMIO Read W @ %"HWADDR_PRIx"\n", addr);
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return 0x0;
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}
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}
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static uint32_t mmio_readl(NeXTState *s, hwaddr addr)
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{
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switch (addr) {
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case 0x7000:
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/* DPRINTF("Read INT status: %x\n", s->int_status); */
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return s->int_status;
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case 0x7800:
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DPRINTF("MMIO Read INT mask: %x\n", s->int_mask);
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return s->int_mask;
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case 0xc000:
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return s->scr1;
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case 0xd000:
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return s->scr2;
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default:
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DPRINTF("MMIO Read L @ %"HWADDR_PRIx"\n", addr);
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return 0x0;
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}
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}
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static void mmio_writeb(NeXTState *s, hwaddr addr, uint32_t val)
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{
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switch (addr) {
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case 0xd003:
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nextscr2_write(s, val, 1);
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break;
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default:
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DPRINTF("MMIO Write B @ %x with %x\n", (unsigned int)addr, val);
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}
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}
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static void mmio_writew(NeXTState *s, hwaddr addr, uint32_t val)
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{
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DPRINTF("MMIO Write W\n");
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}
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static void mmio_writel(NeXTState *s, hwaddr addr, uint32_t val)
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{
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switch (addr) {
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case 0x7000:
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DPRINTF("INT Status old: %x new: %x\n", s->int_status, val);
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s->int_status = val;
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break;
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case 0x7800:
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DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, val);
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s->int_mask = val;
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break;
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case 0xc000:
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DPRINTF("SCR1 Write: %x\n", val);
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break;
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case 0xd000:
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nextscr2_write(s, val, 4);
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break;
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default:
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DPRINTF("MMIO Write l @ %x with %x\n", (unsigned int)addr, val);
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}
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}
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static uint64_t mmio_readfn(void *opaque, hwaddr addr, unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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switch (size) {
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case 1:
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return mmio_readb(ns, addr);
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case 2:
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return mmio_readw(ns, addr);
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case 4:
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return mmio_readl(ns, addr);
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default:
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g_assert_not_reached();
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}
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}
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static void mmio_writefn(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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NeXTState *ns = NEXT_MACHINE(opaque);
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switch (size) {
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case 1:
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mmio_writeb(ns, addr, value);
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break;
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case 2:
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mmio_writew(ns, addr, value);
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break;
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case 4:
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mmio_writel(ns, addr, value);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static const MemoryRegionOps mmio_ops = {
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.read = mmio_readfn,
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.write = mmio_writefn,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint32_t scr_readb(NeXTState *s, hwaddr addr)
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{
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switch (addr) {
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case 0x14108:
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DPRINTF("FD read @ %x\n", (unsigned int)addr);
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return 0x40 | 0x04 | 0x2 | 0x1;
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case 0x14020:
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DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1);
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return s->scsi_csr_1;
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case 0x14021:
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DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2);
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return 0x40;
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/*
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* These 4 registers are the hardware timer, not sure which register
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* is the latch instead of data, but no problems so far
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*/
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case 0x1a000:
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return 0xff & (clock() >> 24);
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case 0x1a001:
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return 0xff & (clock() >> 16);
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case 0x1a002:
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return 0xff & (clock() >> 8);
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case 0x1a003:
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/* Hack: We need to have this change consistently to make it work */
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return 0xFF & clock();
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default:
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DPRINTF("BMAP Read B @ %x\n", (unsigned int)addr);
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return 0;
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}
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}
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static uint32_t scr_readw(NeXTState *s, hwaddr addr)
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{
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DPRINTF("BMAP Read W @ %x\n", (unsigned int)addr);
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return 0;
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}
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static uint32_t scr_readl(NeXTState *s, hwaddr addr)
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{
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DPRINTF("BMAP Read L @ %x\n", (unsigned int)addr);
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return 0;
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}
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#define SCSICSR_ENABLE 0x01
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#define SCSICSR_RESET 0x02 /* reset scsi dma */
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#define SCSICSR_FIFOFL 0x04
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#define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */
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#define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
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#define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
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static void scr_writeb(NeXTState *s, hwaddr addr, uint32_t value)
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{
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switch (addr) {
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case 0x14108:
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DPRINTF("FDCSR Write: %x\n", value);
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if (value == 0x0) {
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/* qemu_irq_raise(s->fd_irq[0]); */
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}
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break;
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case 0x14020: /* SCSI Control Register */
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if (value & SCSICSR_FIFOFL) {
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DPRINTF("SCSICSR FIFO Flush\n");
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/* will have to add another irq to the esp if this is needed */
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/* esp_puflush_fifo(esp_g); */
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/* qemu_irq_pulse(s->scsi_dma); */
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}
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if (value & SCSICSR_ENABLE) {
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DPRINTF("SCSICSR Enable\n");
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/*
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* qemu_irq_raise(s->scsi_dma);
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* s->scsi_csr_1 = 0xc0;
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* s->scsi_csr_1 |= 0x1;
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* qemu_irq_pulse(s->scsi_dma);
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*/
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}
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/*
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* else
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* s->scsi_csr_1 &= ~SCSICSR_ENABLE;
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*/
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if (value & SCSICSR_RESET) {
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DPRINTF("SCSICSR Reset\n");
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/* I think this should set DMADIR. CPUDMA and INTMASK to 0 */
|
|
/* qemu_irq_raise(s->scsi_reset); */
|
|
/* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */
|
|
|
|
}
|
|
if (value & SCSICSR_DMADIR) {
|
|
DPRINTF("SCSICSR DMAdir\n");
|
|
}
|
|
if (value & SCSICSR_CPUDMA) {
|
|
DPRINTF("SCSICSR CPUDMA\n");
|
|
/* qemu_irq_raise(s->scsi_dma); */
|
|
|
|
s->int_status |= 0x4000000;
|
|
} else {
|
|
s->int_status &= ~(0x4000000);
|
|
}
|
|
if (value & SCSICSR_INTMASK) {
|
|
DPRINTF("SCSICSR INTMASK\n");
|
|
/*
|
|
* int_mask &= ~0x1000;
|
|
* s->scsi_csr_1 |= value;
|
|
* s->scsi_csr_1 &= ~SCSICSR_INTMASK;
|
|
* if (s->scsi_queued) {
|
|
* s->scsi_queued = 0;
|
|
* next_irq(s, NEXT_SCSI_I, level);
|
|
* }
|
|
*/
|
|
} else {
|
|
/* int_mask |= 0x1000; */
|
|
}
|
|
if (value & 0x80) {
|
|
/* int_mask |= 0x1000; */
|
|
/* s->scsi_csr_1 |= 0x80; */
|
|
}
|
|
DPRINTF("SCSICSR Write: %x\n", value);
|
|
/* s->scsi_csr_1 = value; */
|
|
return;
|
|
/* Hardware timer latch - not implemented yet */
|
|
case 0x1a000:
|
|
default:
|
|
DPRINTF("BMAP Write B @ %x with %x\n", (unsigned int)addr, value);
|
|
}
|
|
}
|
|
|
|
static void scr_writew(NeXTState *s, hwaddr addr, uint32_t value)
|
|
{
|
|
DPRINTF("BMAP Write W @ %x with %x\n", (unsigned int)addr, value);
|
|
}
|
|
|
|
static void scr_writel(NeXTState *s, hwaddr addr, uint32_t value)
|
|
{
|
|
DPRINTF("BMAP Write L @ %x with %x\n", (unsigned int)addr, value);
|
|
}
|
|
|
|
static uint64_t scr_readfn(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
NeXTState *ns = NEXT_MACHINE(opaque);
|
|
|
|
switch (size) {
|
|
case 1:
|
|
return scr_readb(ns, addr);
|
|
case 2:
|
|
return scr_readw(ns, addr);
|
|
case 4:
|
|
return scr_readl(ns, addr);
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
static void scr_writefn(void *opaque, hwaddr addr, uint64_t value,
|
|
unsigned size)
|
|
{
|
|
NeXTState *ns = NEXT_MACHINE(opaque);
|
|
|
|
switch (size) {
|
|
case 1:
|
|
scr_writeb(ns, addr, value);
|
|
break;
|
|
case 2:
|
|
scr_writew(ns, addr, value);
|
|
break;
|
|
case 4:
|
|
scr_writel(ns, addr, value);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps scr_ops = {
|
|
.read = scr_readfn,
|
|
.write = scr_writefn,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
#define NEXTDMA_SCSI(x) (0x10 + x)
|
|
#define NEXTDMA_FD(x) (0x10 + x)
|
|
#define NEXTDMA_ENTX(x) (0x110 + x)
|
|
#define NEXTDMA_ENRX(x) (0x150 + x)
|
|
#define NEXTDMA_CSR 0x0
|
|
#define NEXTDMA_NEXT 0x4000
|
|
#define NEXTDMA_LIMIT 0x4004
|
|
#define NEXTDMA_START 0x4008
|
|
#define NEXTDMA_STOP 0x400c
|
|
#define NEXTDMA_NEXT_INIT 0x4200
|
|
#define NEXTDMA_SIZE 0x4204
|
|
|
|
static void dma_writel(void *opaque, hwaddr addr, uint64_t value,
|
|
unsigned int size)
|
|
{
|
|
NeXTState *next_state = NEXT_MACHINE(opaque);
|
|
|
|
switch (addr) {
|
|
case NEXTDMA_ENRX(NEXTDMA_CSR):
|
|
if (value & DMA_DEV2M) {
|
|
next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M;
|
|
}
|
|
|
|
if (value & DMA_SETENABLE) {
|
|
/* DPRINTF("SCSI DMA ENABLE\n"); */
|
|
next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE;
|
|
}
|
|
if (value & DMA_SETSUPDATE) {
|
|
next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE;
|
|
}
|
|
if (value & DMA_CLRCOMPLETE) {
|
|
next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE;
|
|
}
|
|
|
|
if (value & DMA_RESET) {
|
|
next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
|
|
DMA_ENABLE | DMA_DEV2M);
|
|
}
|
|
/* DPRINTF("RXCSR \tWrite: %x\n",value); */
|
|
break;
|
|
case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
|
|
next_state->dma[NEXTDMA_ENRX].next_initbuf = value;
|
|
break;
|
|
case NEXTDMA_ENRX(NEXTDMA_NEXT):
|
|
next_state->dma[NEXTDMA_ENRX].next = value;
|
|
break;
|
|
case NEXTDMA_ENRX(NEXTDMA_LIMIT):
|
|
next_state->dma[NEXTDMA_ENRX].limit = value;
|
|
break;
|
|
case NEXTDMA_SCSI(NEXTDMA_CSR):
|
|
if (value & DMA_DEV2M) {
|
|
next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M;
|
|
}
|
|
if (value & DMA_SETENABLE) {
|
|
/* DPRINTF("SCSI DMA ENABLE\n"); */
|
|
next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE;
|
|
}
|
|
if (value & DMA_SETSUPDATE) {
|
|
next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE;
|
|
}
|
|
if (value & DMA_CLRCOMPLETE) {
|
|
next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE;
|
|
}
|
|
|
|
if (value & DMA_RESET) {
|
|
next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
|
|
DMA_ENABLE | DMA_DEV2M);
|
|
/* DPRINTF("SCSI DMA RESET\n"); */
|
|
}
|
|
/* DPRINTF("RXCSR \tWrite: %x\n",value); */
|
|
break;
|
|
|
|
case NEXTDMA_SCSI(NEXTDMA_NEXT):
|
|
next_state->dma[NEXTDMA_SCSI].next = value;
|
|
break;
|
|
|
|
case NEXTDMA_SCSI(NEXTDMA_LIMIT):
|
|
next_state->dma[NEXTDMA_SCSI].limit = value;
|
|
break;
|
|
|
|
case NEXTDMA_SCSI(NEXTDMA_START):
|
|
next_state->dma[NEXTDMA_SCSI].start = value;
|
|
break;
|
|
|
|
case NEXTDMA_SCSI(NEXTDMA_STOP):
|
|
next_state->dma[NEXTDMA_SCSI].stop = value;
|
|
break;
|
|
|
|
case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
|
|
next_state->dma[NEXTDMA_SCSI].next_initbuf = value;
|
|
break;
|
|
|
|
default:
|
|
DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)value);
|
|
}
|
|
}
|
|
|
|
static uint64_t dma_readl(void *opaque, hwaddr addr, unsigned int size)
|
|
{
|
|
NeXTState *next_state = NEXT_MACHINE(opaque);
|
|
|
|
switch (addr) {
|
|
case NEXTDMA_SCSI(NEXTDMA_CSR):
|
|
DPRINTF("SCSI DMA CSR READ\n");
|
|
return next_state->dma[NEXTDMA_SCSI].csr;
|
|
case NEXTDMA_ENRX(NEXTDMA_CSR):
|
|
return next_state->dma[NEXTDMA_ENRX].csr;
|
|
case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
|
|
return next_state->dma[NEXTDMA_ENRX].next_initbuf;
|
|
case NEXTDMA_ENRX(NEXTDMA_NEXT):
|
|
return next_state->dma[NEXTDMA_ENRX].next;
|
|
case NEXTDMA_ENRX(NEXTDMA_LIMIT):
|
|
return next_state->dma[NEXTDMA_ENRX].limit;
|
|
|
|
case NEXTDMA_SCSI(NEXTDMA_NEXT):
|
|
return next_state->dma[NEXTDMA_SCSI].next;
|
|
case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
|
|
return next_state->dma[NEXTDMA_SCSI].next_initbuf;
|
|
case NEXTDMA_SCSI(NEXTDMA_LIMIT):
|
|
return next_state->dma[NEXTDMA_SCSI].limit;
|
|
case NEXTDMA_SCSI(NEXTDMA_START):
|
|
return next_state->dma[NEXTDMA_SCSI].start;
|
|
case NEXTDMA_SCSI(NEXTDMA_STOP):
|
|
return next_state->dma[NEXTDMA_SCSI].stop;
|
|
|
|
default:
|
|
DPRINTF("DMA read @ %x\n", (unsigned int)addr);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* once the csr's are done, subtract 0x3FEC from the addr, and that will
|
|
* normalize the upper registers
|
|
*/
|
|
}
|
|
|
|
static const MemoryRegionOps dma_ops = {
|
|
.read = dma_readl,
|
|
.write = dma_writel,
|
|
.impl.min_access_size = 4,
|
|
.valid.min_access_size = 4,
|
|
.valid.max_access_size = 4,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
/*
|
|
* TODO: set the shift numbers as values in the enum, so the first switch
|
|
* will not be needed
|
|
*/
|
|
void next_irq(void *opaque, int number, int level)
|
|
{
|
|
M68kCPU *cpu = opaque;
|
|
int shift = 0;
|
|
NeXTState *ns = NEXT_MACHINE(qdev_get_machine());
|
|
|
|
/* first switch sets interupt status */
|
|
/* DPRINTF("IRQ %i\n",number); */
|
|
switch (number) {
|
|
/* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
|
|
case NEXT_FD_I:
|
|
shift = 7;
|
|
break;
|
|
case NEXT_KBD_I:
|
|
shift = 3;
|
|
break;
|
|
case NEXT_PWR_I:
|
|
shift = 2;
|
|
break;
|
|
case NEXT_ENRX_I:
|
|
shift = 9;
|
|
break;
|
|
case NEXT_ENTX_I:
|
|
shift = 10;
|
|
break;
|
|
case NEXT_SCSI_I:
|
|
shift = 12;
|
|
break;
|
|
case NEXT_CLK_I:
|
|
shift = 5;
|
|
break;
|
|
|
|
/* level 5 - scc (serial) */
|
|
case NEXT_SCC_I:
|
|
shift = 17;
|
|
break;
|
|
|
|
/* level 6 - audio etherrx/tx dma */
|
|
case NEXT_ENTX_DMA_I:
|
|
shift = 28;
|
|
break;
|
|
case NEXT_ENRX_DMA_I:
|
|
shift = 27;
|
|
break;
|
|
case NEXT_SCSI_DMA_I:
|
|
shift = 26;
|
|
break;
|
|
case NEXT_SND_I:
|
|
shift = 23;
|
|
break;
|
|
case NEXT_SCC_DMA_I:
|
|
shift = 21;
|
|
break;
|
|
|
|
}
|
|
/*
|
|
* this HAS to be wrong, the interrupt handlers in mach and together
|
|
* int_status and int_mask and return if there is a hit
|
|
*/
|
|
if (ns->int_mask & (1 << shift)) {
|
|
DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc);
|
|
/* return; */
|
|
}
|
|
|
|
/* second switch triggers the correct interrupt */
|
|
if (level) {
|
|
ns->int_status |= 1 << shift;
|
|
|
|
switch (number) {
|
|
/* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
|
|
case NEXT_FD_I:
|
|
case NEXT_KBD_I:
|
|
case NEXT_PWR_I:
|
|
case NEXT_ENRX_I:
|
|
case NEXT_ENTX_I:
|
|
case NEXT_SCSI_I:
|
|
case NEXT_CLK_I:
|
|
m68k_set_irq_level(cpu, 3, 27);
|
|
break;
|
|
|
|
/* level 5 - scc (serial) */
|
|
case NEXT_SCC_I:
|
|
m68k_set_irq_level(cpu, 5, 29);
|
|
break;
|
|
|
|
/* level 6 - audio etherrx/tx dma */
|
|
case NEXT_ENTX_DMA_I:
|
|
case NEXT_ENRX_DMA_I:
|
|
case NEXT_SCSI_DMA_I:
|
|
case NEXT_SND_I:
|
|
case NEXT_SCC_DMA_I:
|
|
m68k_set_irq_level(cpu, 6, 30);
|
|
break;
|
|
}
|
|
} else {
|
|
ns->int_status &= ~(1 << shift);
|
|
cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
|
|
}
|
|
}
|
|
|
|
static void next_serial_irq(void *opaque, int n, int level)
|
|
{
|
|
/* DPRINTF("SCC IRQ NUM %i\n",n); */
|
|
if (n) {
|
|
next_irq(opaque, NEXT_SCC_DMA_I, level);
|
|
} else {
|
|
next_irq(opaque, NEXT_SCC_I, level);
|
|
}
|
|
}
|
|
|
|
static void next_escc_init(M68kCPU *cpu)
|
|
{
|
|
qemu_irq *ser_irq = qemu_allocate_irqs(next_serial_irq, cpu, 2);
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
|
|
dev = qdev_create(NULL, TYPE_ESCC);
|
|
qdev_prop_set_uint32(dev, "disabled", 0);
|
|
qdev_prop_set_uint32(dev, "frequency", 9600 * 384);
|
|
qdev_prop_set_uint32(dev, "it_shift", 0);
|
|
qdev_prop_set_bit(dev, "bit_swap", true);
|
|
qdev_prop_set_chr(dev, "chrB", serial_hd(1));
|
|
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
|
|
qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
|
|
qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
|
|
qdev_init_nofail(dev);
|
|
|
|
s = SYS_BUS_DEVICE(dev);
|
|
sysbus_connect_irq(s, 0, ser_irq[0]);
|
|
sysbus_connect_irq(s, 1, ser_irq[1]);
|
|
sysbus_mmio_map(s, 0, 0x2118000);
|
|
}
|
|
|
|
static void next_cube_init(MachineState *machine)
|
|
{
|
|
M68kCPU *cpu;
|
|
CPUM68KState *env;
|
|
MemoryRegion *rom = g_new(MemoryRegion, 1);
|
|
MemoryRegion *mmiomem = g_new(MemoryRegion, 1);
|
|
MemoryRegion *scrmem = g_new(MemoryRegion, 1);
|
|
MemoryRegion *dmamem = g_new(MemoryRegion, 1);
|
|
MemoryRegion *bmapm1 = g_new(MemoryRegion, 1);
|
|
MemoryRegion *bmapm2 = g_new(MemoryRegion, 1);
|
|
MemoryRegion *sysmem = get_system_memory();
|
|
NeXTState *ns = NEXT_MACHINE(machine);
|
|
DeviceState *dev;
|
|
|
|
/* Initialize the cpu core */
|
|
cpu = M68K_CPU(cpu_create(machine->cpu_type));
|
|
if (!cpu) {
|
|
error_report("Unable to find m68k CPU definition");
|
|
exit(1);
|
|
}
|
|
env = &cpu->env;
|
|
|
|
/* Initialize CPU registers. */
|
|
env->vbr = 0;
|
|
env->sr = 0x2700;
|
|
|
|
/* Set internal registers to initial values */
|
|
/* 0x0000XX00 << vital bits */
|
|
ns->scr1 = 0x00011102;
|
|
ns->scr2 = 0x00ff0c80;
|
|
ns->rtc.status = 0x90;
|
|
|
|
/* Load RTC RAM - TODO: provide possibility to load contents from file */
|
|
memcpy(ns->rtc.ram, rtc_ram2, 32);
|
|
|
|
/* 64MB RAM starting at 0x04000000 */
|
|
memory_region_add_subregion(sysmem, 0x04000000, machine->ram);
|
|
|
|
/* Framebuffer */
|
|
dev = qdev_create(NULL, TYPE_NEXTFB);
|
|
qdev_init_nofail(dev);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000);
|
|
|
|
/* MMIO */
|
|
memory_region_init_io(mmiomem, NULL, &mmio_ops, machine, "next.mmio",
|
|
0xD0000);
|
|
memory_region_add_subregion(sysmem, 0x02000000, mmiomem);
|
|
|
|
/* BMAP memory */
|
|
memory_region_init_ram_shared_nomigrate(bmapm1, NULL, "next.bmapmem", 64,
|
|
true, &error_fatal);
|
|
memory_region_add_subregion(sysmem, 0x020c0000, bmapm1);
|
|
/* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */
|
|
memory_region_init_alias(bmapm2, NULL, "next.bmapmem2", bmapm1, 0x0, 64);
|
|
memory_region_add_subregion(sysmem, 0x820c0000, bmapm2);
|
|
|
|
/* BMAP IO - acts as a catch-all for now */
|
|
memory_region_init_io(scrmem, NULL, &scr_ops, machine, "next.scr",
|
|
0x20000);
|
|
memory_region_add_subregion(sysmem, 0x02100000, scrmem);
|
|
|
|
/* KBD */
|
|
dev = qdev_create(NULL, TYPE_NEXTKBD);
|
|
qdev_init_nofail(dev);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000);
|
|
|
|
/* Load ROM here */
|
|
if (bios_name == NULL) {
|
|
bios_name = ROM_FILE;
|
|
}
|
|
/* still not sure if the rom should also be mapped at 0x0*/
|
|
memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal);
|
|
memory_region_add_subregion(sysmem, 0x01000000, rom);
|
|
if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) {
|
|
if (!qtest_enabled()) {
|
|
error_report("Failed to load firmware '%s'.", bios_name);
|
|
}
|
|
} else {
|
|
uint8_t *ptr;
|
|
/* Initial PC is always at offset 4 in firmware binaries */
|
|
ptr = rom_ptr(0x01000004, 4);
|
|
g_assert(ptr != NULL);
|
|
env->pc = ldl_p(ptr);
|
|
if (env->pc >= 0x01020000) {
|
|
error_report("'%s' does not seem to be a valid firmware image.",
|
|
bios_name);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* Serial */
|
|
next_escc_init(cpu);
|
|
|
|
/* TODO: */
|
|
/* Network */
|
|
/* SCSI */
|
|
|
|
/* DMA */
|
|
memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000);
|
|
memory_region_add_subregion(sysmem, 0x02000000, dmamem);
|
|
}
|
|
|
|
static void next_machine_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "NeXT Cube";
|
|
mc->init = next_cube_init;
|
|
mc->default_ram_size = RAM_SIZE;
|
|
mc->default_ram_id = "next.ram";
|
|
mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
|
|
}
|
|
|
|
static const TypeInfo next_typeinfo = {
|
|
.name = TYPE_NEXT_MACHINE,
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = next_machine_class_init,
|
|
.instance_size = sizeof(NeXTState),
|
|
};
|
|
|
|
static void next_register_type(void)
|
|
{
|
|
type_register_static(&next_typeinfo);
|
|
}
|
|
|
|
type_init(next_register_type)
|