Those reset values have been extracted from a Raspberry Pi 3 model B v1.2, using the 2020-08-20 version of raspios. The dump was done using the debugfs interface of the CPRMAN driver in Linux (under '/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels and muxes) can be observed by reading the 'regdump' file (e.g. 'plla/regdump'). Those values are set by the Raspberry Pi firmware at boot time (Linux expects them to be set when it boots up). Some stages are not exposed by the Linux driver (e.g. the PLL B). For those, the reset values are unknown and left to 0 which implies a disabled output. Once booted in QEMU, the final clock tree is very similar to the one visible on real hardware. The differences come from some unimplemented devices for which the driver simply disable the corresponding clock. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
809 lines
22 KiB
C
809 lines
22 KiB
C
/*
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* BCM2835 CPRMAN clock manager
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*
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* Copyright (c) 2020 Luc Michel <luc@lmichel.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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/*
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* This peripheral is roughly divided into 3 main parts:
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* - the PLLs
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* - the PLL channels
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* - the clock muxes
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*
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* A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more
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* channels. Those channel are then connected to the clock muxes. Each mux has
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* multiples sources (usually the xosc, some of the PLL channels and some "test
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* debug" clocks). A mux is configured to select a given source through its
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* control register. Each mux has one output clock that also goes out of the
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* CPRMAN. This output clock usually connects to another peripheral in the SoC
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* (so a given mux is dedicated to a peripheral).
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*
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* At each level (PLL, channel and mux), the clock can be altered through
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* dividers (and multipliers in case of the PLLs), and can be disabled (in this
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* case, the next levels see no clock).
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*
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* This can be sum-up as follows (this is an example and not the actual BCM2835
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* clock tree):
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*
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* /-->[PLL]-|->[PLL channel]--... [mux]--> to peripherals
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* | |->[PLL channel] muxes takes [mux]
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* | \->[PLL channel] inputs from [mux]
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* | some channels [mux]
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* [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux]
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* | \->[PLL channel] ...-->[mux]
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* | [mux]
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* \-->[PLL]--->[PLL channel] [mux]
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*
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* The page at https://elinux.org/The_Undocumented_Pi gives the actual clock
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* tree configuration.
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*
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* The CPRMAN exposes clock outputs with the name of the clock mux suffixed
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* with "-out" (e.g. "uart-out", "h264-out", ...).
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/bcm2835_cprman.h"
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#include "hw/misc/bcm2835_cprman_internals.h"
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#include "trace.h"
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/* PLL */
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static void pll_reset(DeviceState *dev)
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{
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CprmanPllState *s = CPRMAN_PLL(dev);
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const PLLResetInfo *info = &PLL_RESET_INFO[s->id];
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*s->reg_cm = info->cm;
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*s->reg_a2w_ctrl = info->a2w_ctrl;
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memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana));
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*s->reg_a2w_frac = info->a2w_frac;
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}
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static bool pll_is_locked(const CprmanPllState *pll)
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{
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return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN)
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&& !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST);
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}
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static void pll_update(CprmanPllState *pll)
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{
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uint64_t freq, ndiv, fdiv, pdiv;
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if (!pll_is_locked(pll)) {
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clock_update(pll->out, 0);
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return;
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}
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pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV);
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if (!pdiv) {
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clock_update(pll->out, 0);
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return;
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}
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ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV);
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fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC);
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if (pll->reg_a2w_ana[1] & pll->prediv_mask) {
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/* The prescaler doubles the parent frequency */
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ndiv *= 2;
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fdiv *= 2;
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}
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/*
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* We have a multiplier with an integer part (ndiv) and a fractional part
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* (fdiv), and a divider (pdiv).
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*/
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freq = clock_get_hz(pll->xosc_in) *
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((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv);
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freq /= pdiv;
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freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH;
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clock_update_hz(pll->out, freq);
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}
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static void pll_xosc_update(void *opaque)
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{
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pll_update(CPRMAN_PLL(opaque));
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}
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static void pll_init(Object *obj)
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{
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CprmanPllState *s = CPRMAN_PLL(obj);
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s->xosc_in = qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_update, s);
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static const VMStateDescription pll_vmstate = {
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.name = TYPE_CPRMAN_PLL,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_CLOCK(xosc_in, CprmanPllState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pll_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = pll_reset;
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dc->vmsd = &pll_vmstate;
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}
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static const TypeInfo cprman_pll_info = {
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.name = TYPE_CPRMAN_PLL,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CprmanPllState),
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.class_init = pll_class_init,
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.instance_init = pll_init,
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};
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/* PLL channel */
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static void pll_channel_reset(DeviceState *dev)
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{
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CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(dev);
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const PLLChannelResetInfo *info = &PLL_CHANNEL_RESET_INFO[s->id];
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*s->reg_a2w_ctrl = info->a2w_ctrl;
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}
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static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
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{
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/*
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* XXX I'm not sure of the purpose of the LOAD field. The Linux driver does
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* not set it when enabling the channel, but does clear it when disabling
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* it.
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*/
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return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE)
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&& !(*channel->reg_cm & channel->hold_mask);
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}
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static void pll_channel_update(CprmanPllChannelState *channel)
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{
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uint64_t freq, div;
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if (!pll_channel_is_enabled(channel)) {
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clock_update(channel->out, 0);
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return;
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}
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div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV);
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if (!div) {
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/*
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* It seems that when the divider value is 0, it is considered as
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* being maximum by the hardware (see the Linux driver).
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*/
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div = R_A2W_PLLx_CHANNELy_DIV_MASK;
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}
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/* Some channels have an additional fixed divider */
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freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider);
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clock_update_hz(channel->out, freq);
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}
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/* Update a PLL and all its channels */
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static void pll_update_all_channels(BCM2835CprmanState *s,
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CprmanPllState *pll)
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{
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size_t i;
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pll_update(pll);
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for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
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CprmanPllChannelState *channel = &s->channels[i];
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if (channel->parent == pll->id) {
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pll_channel_update(channel);
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}
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}
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}
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static void pll_channel_pll_in_update(void *opaque)
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{
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pll_channel_update(CPRMAN_PLL_CHANNEL(opaque));
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}
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static void pll_channel_init(Object *obj)
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{
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CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(obj);
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s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in",
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pll_channel_pll_in_update, s);
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static const VMStateDescription pll_channel_vmstate = {
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.name = TYPE_CPRMAN_PLL_CHANNEL,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_CLOCK(pll_in, CprmanPllChannelState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pll_channel_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = pll_channel_reset;
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dc->vmsd = &pll_channel_vmstate;
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}
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static const TypeInfo cprman_pll_channel_info = {
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.name = TYPE_CPRMAN_PLL_CHANNEL,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CprmanPllChannelState),
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.class_init = pll_channel_class_init,
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.instance_init = pll_channel_init,
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};
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/* clock mux */
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static bool clock_mux_is_enabled(CprmanClockMuxState *mux)
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{
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return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE);
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}
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static void clock_mux_update(CprmanClockMuxState *mux)
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{
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uint64_t freq;
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uint32_t div, src = FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC);
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bool enabled = clock_mux_is_enabled(mux);
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*mux->reg_ctl = FIELD_DP32(*mux->reg_ctl, CM_CLOCKx_CTL, BUSY, enabled);
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if (!enabled) {
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clock_update(mux->out, 0);
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return;
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}
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freq = clock_get_hz(mux->srcs[src]);
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if (mux->int_bits == 0 && mux->frac_bits == 0) {
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clock_update_hz(mux->out, freq);
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return;
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}
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/*
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* The divider has an integer and a fractional part. The size of each part
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* varies with the muxes (int_bits and frac_bits). Both parts are
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* concatenated, with the integer part always starting at bit 12.
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*
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* 31 12 11 0
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* ------------------------------
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* CM_DIV | | int | frac | |
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* ------------------------------
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* <-----> <------>
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* int_bits frac_bits
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*/
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div = extract32(*mux->reg_div,
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R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits,
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mux->int_bits + mux->frac_bits);
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if (!div) {
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clock_update(mux->out, 0);
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return;
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}
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freq = muldiv64(freq, 1 << mux->frac_bits, div);
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clock_update_hz(mux->out, freq);
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}
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static void clock_mux_src_update(void *opaque)
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{
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CprmanClockMuxState **backref = opaque;
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CprmanClockMuxState *s = *backref;
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CprmanClockMuxSource src = backref - s->backref;
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if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) != src) {
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return;
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}
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clock_mux_update(s);
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}
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static void clock_mux_reset(DeviceState *dev)
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{
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CprmanClockMuxState *clock = CPRMAN_CLOCK_MUX(dev);
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const ClockMuxResetInfo *info = &CLOCK_MUX_RESET_INFO[clock->id];
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*clock->reg_ctl = info->cm_ctl;
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*clock->reg_div = info->cm_div;
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}
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static void clock_mux_init(Object *obj)
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{
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CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj);
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size_t i;
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
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char *name = g_strdup_printf("srcs[%zu]", i);
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s->backref[i] = s;
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s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
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clock_mux_src_update,
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&s->backref[i]);
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g_free(name);
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}
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static const VMStateDescription clock_mux_vmstate = {
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.name = TYPE_CPRMAN_CLOCK_MUX,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState,
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CPRMAN_NUM_CLOCK_MUX_SRC),
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VMSTATE_END_OF_LIST()
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}
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};
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static void clock_mux_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = clock_mux_reset;
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dc->vmsd = &clock_mux_vmstate;
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}
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static const TypeInfo cprman_clock_mux_info = {
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.name = TYPE_CPRMAN_CLOCK_MUX,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CprmanClockMuxState),
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.class_init = clock_mux_class_init,
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.instance_init = clock_mux_init,
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};
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/* DSI0HSCK mux */
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static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s)
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{
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bool src_is_plld = FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD);
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Clock *src = src_is_plld ? s->plld_in : s->plla_in;
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clock_update(s->out, clock_get(src));
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}
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static void dsi0hsck_mux_in_update(void *opaque)
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{
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dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque));
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}
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static void dsi0hsck_mux_init(Object *obj)
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{
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CprmanDsi0HsckMuxState *s = CPRMAN_DSI0HSCK_MUX(obj);
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DeviceState *dev = DEVICE(obj);
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s->plla_in = qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_update, s);
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s->plld_in = qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_update, s);
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static const VMStateDescription dsi0hsck_mux_vmstate = {
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.name = TYPE_CPRMAN_DSI0HSCK_MUX,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState),
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VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &dsi0hsck_mux_vmstate;
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}
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static const TypeInfo cprman_dsi0hsck_mux_info = {
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.name = TYPE_CPRMAN_DSI0HSCK_MUX,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CprmanDsi0HsckMuxState),
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.class_init = dsi0hsck_mux_class_init,
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.instance_init = dsi0hsck_mux_init,
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};
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/* CPRMAN "top level" model */
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static uint32_t get_cm_lock(const BCM2835CprmanState *s)
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{
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static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] = {
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[CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT,
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[CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT,
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[CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT,
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[CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT,
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[CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT,
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};
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uint32_t r = 0;
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size_t i;
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for (i = 0; i < CPRMAN_NUM_PLL; i++) {
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r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i];
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}
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return r;
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}
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static uint64_t cprman_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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BCM2835CprmanState *s = CPRMAN(opaque);
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uint64_t r = 0;
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size_t idx = offset / sizeof(uint32_t);
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switch (idx) {
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case R_CM_LOCK:
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r = get_cm_lock(s);
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break;
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default:
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r = s->regs[idx];
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}
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trace_bcm2835_cprman_read(offset, r);
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return r;
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}
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static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s,
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size_t idx)
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{
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size_t i;
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for (i = 0; i < CPRMAN_NUM_PLL; i++) {
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if (PLL_INIT_INFO[i].cm_offset == idx) {
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pll_update_all_channels(s, &s->plls[i]);
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return;
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}
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}
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}
|
|
|
|
static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx)
|
|
{
|
|
size_t i;
|
|
|
|
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
|
|
if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset == idx) {
|
|
pll_channel_update(&s->channels[i]);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx)
|
|
{
|
|
size_t i;
|
|
|
|
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
|
|
if ((CLOCK_MUX_INIT_INFO[i].cm_offset == idx) ||
|
|
(CLOCK_MUX_INIT_INFO[i].cm_offset + 4 == idx)) {
|
|
/* matches CM_CTL or CM_DIV mux register */
|
|
clock_mux_update(&s->clock_muxes[i]);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
#define CASE_PLL_A2W_REGS(pll_) \
|
|
case R_A2W_ ## pll_ ## _CTRL: \
|
|
case R_A2W_ ## pll_ ## _ANA0: \
|
|
case R_A2W_ ## pll_ ## _ANA1: \
|
|
case R_A2W_ ## pll_ ## _ANA2: \
|
|
case R_A2W_ ## pll_ ## _ANA3: \
|
|
case R_A2W_ ## pll_ ## _FRAC
|
|
|
|
static void cprman_write(void *opaque, hwaddr offset,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
BCM2835CprmanState *s = CPRMAN(opaque);
|
|
size_t idx = offset / sizeof(uint32_t);
|
|
|
|
if (FIELD_EX32(value, CPRMAN, PASSWORD) != CPRMAN_PASSWORD) {
|
|
trace_bcm2835_cprman_write_invalid_magic(offset, value);
|
|
return;
|
|
}
|
|
|
|
value &= ~R_CPRMAN_PASSWORD_MASK;
|
|
|
|
trace_bcm2835_cprman_write(offset, value);
|
|
s->regs[idx] = value;
|
|
|
|
switch (idx) {
|
|
case R_CM_PLLA ... R_CM_PLLH:
|
|
case R_CM_PLLB:
|
|
/*
|
|
* A given CM_PLLx register is shared by both the PLL and the channels
|
|
* of this PLL.
|
|
*/
|
|
update_pll_and_channels_from_cm(s, idx);
|
|
break;
|
|
|
|
CASE_PLL_A2W_REGS(PLLA) :
|
|
pll_update(&s->plls[CPRMAN_PLLA]);
|
|
break;
|
|
|
|
CASE_PLL_A2W_REGS(PLLC) :
|
|
pll_update(&s->plls[CPRMAN_PLLC]);
|
|
break;
|
|
|
|
CASE_PLL_A2W_REGS(PLLD) :
|
|
pll_update(&s->plls[CPRMAN_PLLD]);
|
|
break;
|
|
|
|
CASE_PLL_A2W_REGS(PLLH) :
|
|
pll_update(&s->plls[CPRMAN_PLLH]);
|
|
break;
|
|
|
|
CASE_PLL_A2W_REGS(PLLB) :
|
|
pll_update(&s->plls[CPRMAN_PLLB]);
|
|
break;
|
|
|
|
case R_A2W_PLLA_DSI0:
|
|
case R_A2W_PLLA_CORE:
|
|
case R_A2W_PLLA_PER:
|
|
case R_A2W_PLLA_CCP2:
|
|
case R_A2W_PLLC_CORE2:
|
|
case R_A2W_PLLC_CORE1:
|
|
case R_A2W_PLLC_PER:
|
|
case R_A2W_PLLC_CORE0:
|
|
case R_A2W_PLLD_DSI0:
|
|
case R_A2W_PLLD_CORE:
|
|
case R_A2W_PLLD_PER:
|
|
case R_A2W_PLLD_DSI1:
|
|
case R_A2W_PLLH_AUX:
|
|
case R_A2W_PLLH_RCAL:
|
|
case R_A2W_PLLH_PIX:
|
|
case R_A2W_PLLB_ARM:
|
|
update_channel_from_a2w(s, idx);
|
|
break;
|
|
|
|
case R_CM_GNRICCTL ... R_CM_SMIDIV:
|
|
case R_CM_TCNTCNT ... R_CM_VECDIV:
|
|
case R_CM_PULSECTL ... R_CM_PULSEDIV:
|
|
case R_CM_SDCCTL ... R_CM_ARMCTL:
|
|
case R_CM_AVEOCTL ... R_CM_EMMCDIV:
|
|
case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
|
|
update_mux_from_cm(s, idx);
|
|
break;
|
|
|
|
case R_CM_DSI0HSCK:
|
|
dsi0hsck_mux_update(&s->dsi0hsck_mux);
|
|
break;
|
|
}
|
|
}
|
|
|
|
#undef CASE_PLL_A2W_REGS
|
|
|
|
static const MemoryRegionOps cprman_ops = {
|
|
.read = cprman_read,
|
|
.write = cprman_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid = {
|
|
/*
|
|
* Although this hasn't been checked against real hardware, nor the
|
|
* information can be found in a datasheet, it seems reasonable because
|
|
* of the "PASSWORD" magic value found in every registers.
|
|
*/
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
.unaligned = false,
|
|
},
|
|
.impl = {
|
|
.max_access_size = 4,
|
|
},
|
|
};
|
|
|
|
static void cprman_reset(DeviceState *dev)
|
|
{
|
|
BCM2835CprmanState *s = CPRMAN(dev);
|
|
size_t i;
|
|
|
|
memset(s->regs, 0, sizeof(s->regs));
|
|
|
|
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
|
|
device_cold_reset(DEVICE(&s->plls[i]));
|
|
}
|
|
|
|
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
|
|
device_cold_reset(DEVICE(&s->channels[i]));
|
|
}
|
|
|
|
device_cold_reset(DEVICE(&s->dsi0hsck_mux));
|
|
|
|
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
|
|
device_cold_reset(DEVICE(&s->clock_muxes[i]));
|
|
}
|
|
|
|
clock_update_hz(s->xosc, s->xosc_freq);
|
|
}
|
|
|
|
static void cprman_init(Object *obj)
|
|
{
|
|
BCM2835CprmanState *s = CPRMAN(obj);
|
|
size_t i;
|
|
|
|
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
|
|
object_initialize_child(obj, PLL_INIT_INFO[i].name,
|
|
&s->plls[i], TYPE_CPRMAN_PLL);
|
|
set_pll_init_info(s, &s->plls[i], i);
|
|
}
|
|
|
|
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
|
|
object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name,
|
|
&s->channels[i],
|
|
TYPE_CPRMAN_PLL_CHANNEL);
|
|
set_pll_channel_init_info(s, &s->channels[i], i);
|
|
}
|
|
|
|
object_initialize_child(obj, "dsi0hsck-mux",
|
|
&s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX);
|
|
s->dsi0hsck_mux.reg_cm = &s->regs[R_CM_DSI0HSCK];
|
|
|
|
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
|
|
char *alias;
|
|
|
|
object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name,
|
|
&s->clock_muxes[i],
|
|
TYPE_CPRMAN_CLOCK_MUX);
|
|
set_clock_mux_init_info(s, &s->clock_muxes[i], i);
|
|
|
|
/* Expose muxes output as CPRMAN outputs */
|
|
alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name);
|
|
qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias);
|
|
g_free(alias);
|
|
}
|
|
|
|
s->xosc = clock_new(obj, "xosc");
|
|
s->gnd = clock_new(obj, "gnd");
|
|
|
|
clock_set(s->gnd, 0);
|
|
|
|
memory_region_init_io(&s->iomem, obj, &cprman_ops,
|
|
s, "bcm2835-cprman", 0x2000);
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
|
|
}
|
|
|
|
static void connect_mux_sources(BCM2835CprmanState *s,
|
|
CprmanClockMuxState *mux,
|
|
const CprmanPllChannel *clk_mapping)
|
|
{
|
|
size_t i;
|
|
Clock *td0 = s->clock_muxes[CPRMAN_CLOCK_TD0].out;
|
|
Clock *td1 = s->clock_muxes[CPRMAN_CLOCK_TD1].out;
|
|
|
|
/* For sources from 0 to 3. Source 4 to 9 are mux specific */
|
|
Clock * const CLK_SRC_MAPPING[] = {
|
|
[CPRMAN_CLOCK_SRC_GND] = s->gnd,
|
|
[CPRMAN_CLOCK_SRC_XOSC] = s->xosc,
|
|
[CPRMAN_CLOCK_SRC_TD0] = td0,
|
|
[CPRMAN_CLOCK_SRC_TD1] = td1,
|
|
};
|
|
|
|
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
|
|
CprmanPllChannel mapping = clk_mapping[i];
|
|
Clock *src;
|
|
|
|
if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) {
|
|
src = s->gnd;
|
|
} else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) {
|
|
src = s->dsi0hsck_mux.out;
|
|
} else if (i < CPRMAN_CLOCK_SRC_PLLA) {
|
|
src = CLK_SRC_MAPPING[i];
|
|
} else {
|
|
src = s->channels[mapping].out;
|
|
}
|
|
|
|
clock_set_source(mux->srcs[i], src);
|
|
}
|
|
}
|
|
|
|
static void cprman_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
BCM2835CprmanState *s = CPRMAN(dev);
|
|
size_t i;
|
|
|
|
for (i = 0; i < CPRMAN_NUM_PLL; i++) {
|
|
CprmanPllState *pll = &s->plls[i];
|
|
|
|
clock_set_source(pll->xosc_in, s->xosc);
|
|
|
|
if (!qdev_realize(DEVICE(pll), NULL, errp)) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
|
|
CprmanPllChannelState *channel = &s->channels[i];
|
|
CprmanPll parent = PLL_CHANNEL_INIT_INFO[i].parent;
|
|
Clock *parent_clk = s->plls[parent].out;
|
|
|
|
clock_set_source(channel->pll_in, parent_clk);
|
|
|
|
if (!qdev_realize(DEVICE(channel), NULL, errp)) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
clock_set_source(s->dsi0hsck_mux.plla_in,
|
|
s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out);
|
|
clock_set_source(s->dsi0hsck_mux.plld_in,
|
|
s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out);
|
|
|
|
if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) {
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
|
|
CprmanClockMuxState *clock_mux = &s->clock_muxes[i];
|
|
|
|
connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping);
|
|
|
|
if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static const VMStateDescription cprman_vmstate = {
|
|
.name = TYPE_BCM2835_CPRMAN,
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32_ARRAY(regs, BCM2835CprmanState, CPRMAN_NUM_REGS),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property cprman_properties[] = {
|
|
DEFINE_PROP_UINT32("xosc-freq-hz", BCM2835CprmanState, xosc_freq, 19200000),
|
|
DEFINE_PROP_END_OF_LIST()
|
|
};
|
|
|
|
static void cprman_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = cprman_realize;
|
|
dc->reset = cprman_reset;
|
|
dc->vmsd = &cprman_vmstate;
|
|
device_class_set_props(dc, cprman_properties);
|
|
}
|
|
|
|
static const TypeInfo cprman_info = {
|
|
.name = TYPE_BCM2835_CPRMAN,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(BCM2835CprmanState),
|
|
.class_init = cprman_class_init,
|
|
.instance_init = cprman_init,
|
|
};
|
|
|
|
static void cprman_register_types(void)
|
|
{
|
|
type_register_static(&cprman_info);
|
|
type_register_static(&cprman_pll_info);
|
|
type_register_static(&cprman_pll_channel_info);
|
|
type_register_static(&cprman_clock_mux_info);
|
|
type_register_static(&cprman_dsi0hsck_mux_info);
|
|
}
|
|
|
|
type_init(cprman_register_types);
|