adbb3df08e
DFPU doesn't have pre-increment FP load/store opcodes, it has post-increment opcodes instead. Test increment opcodes present in the current config. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
144 lines
2.4 KiB
ArmAsm
144 lines
2.4 KiB
ArmAsm
#include "macros.inc"
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#include "fpu.h"
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test_suite lsc
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#if XCHAL_HAVE_FP
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test lsi
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movi a2, 1
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wsr a2, cpenable
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movi a2, 1f
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lsi f1, a2, 4
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#if DFPU
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lsi f2, a2, 8
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lsip f0, a2, 8
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#else
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lsi f0, a2, 0
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lsiu f2, a2, 8
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#endif
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movi a3, 1f + 8
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assert eq, a2, a3
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rfr a2, f0
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movi a3, 0x3f800000
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assert eq, a2, a3
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rfr a2, f1
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movi a3, 0x40000000
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assert eq, a2, a3
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rfr a2, f2
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movi a3, 0x40400000
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assert eq, a2, a3
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.data
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.align 4
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1:
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.float 1, 2, 3
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.text
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test_end
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test ssi
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movi a2, 1f
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movi a3, 0x40800000
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wfr f3, a3
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movi a3, 0x40a00000
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wfr f4, a3
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movi a3, 0x40c00000
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wfr f5, a3
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ssi f4, a2, 4
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#if DFPU
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ssi f5, a2, 8
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ssip f3, a2, 8
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#else
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ssi f3, a2, 0
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ssiu f5, a2, 8
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#endif
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movi a3, 1f + 8
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assert eq, a2, a3
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l32i a4, a2, -8
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movi a3, 0x40800000
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assert eq, a4, a3
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l32i a4, a2, -4
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movi a3, 0x40a00000
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assert eq, a4, a3
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l32i a4, a2, 0
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movi a3, 0x40c00000
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assert eq, a4, a3
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.data
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.align 4
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1:
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.float 0, 0, 0
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.text
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test_end
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test lsx
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movi a2, 1f
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movi a3, 0
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movi a4, 4
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movi a5, 8
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lsx f7, a2, a4
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#if DFPU
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lsx f8, a2, a5
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lsxp f6, a2, a5
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#else
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lsx f6, a2, a3
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lsxu f8, a2, a5
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#endif
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movi a3, 1f + 8
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assert eq, a2, a3
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rfr a2, f6
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movi a3, 0x40e00000
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assert eq, a2, a3
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rfr a2, f7
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movi a3, 0x41000000
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assert eq, a2, a3
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rfr a2, f8
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movi a3, 0x41100000
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assert eq, a2, a3
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.data
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.align 4
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1:
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.float 7, 8, 9
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.text
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test_end
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test ssx
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movi a2, 1f
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movi a4, 0x41200000
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wfr f9, a4
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movi a4, 0x41300000
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wfr f10, a4
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movi a4, 0x41400000
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wfr f11, a4
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movi a3, 0
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movi a4, 4
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movi a5, 8
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ssx f10, a2, a4
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#if DFPU
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ssx f11, a2, a5
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ssxp f9, a2, a5
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#else
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ssx f9, a2, a3
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ssxu f11, a2, a5
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#endif
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movi a3, 1f + 8
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assert eq, a2, a3
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l32i a4, a2, -8
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movi a3, 0x41200000
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assert eq, a4, a3
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l32i a4, a2, -4
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movi a3, 0x41300000
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assert eq, a4, a3
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l32i a4, a2, 0
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movi a3, 0x41400000
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assert eq, a4, a3
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.data
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.align 4
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1:
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.float 0, 0, 0
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.text
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test_end
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#endif
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test_suite_end
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