The way the XICS and the XIVE devices are initialized follows the same pattern. First, try to connect to the KVM device and if not possible fallback on the emulated device, unless a kernel_irqchip is required. The spapr_irq_init_device() routine implements this sequence in generic way using new sPAPR IRQ handlers ->init_emu() and ->init_kvm(). The XIVE init sequence is moved under the associated sPAPR IRQ ->init() handler. This will change again when KVM support is added for the dual interrupt mode. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190513084245.25755-12-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
815 lines
22 KiB
C
815 lines
22 KiB
C
/*
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* QEMU PowerPC sPAPR IRQ interface
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "hw/ppc/spapr_xive.h"
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#include "hw/ppc/xics.h"
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#include "hw/ppc/xics_spapr.h"
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#include "cpu-models.h"
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#include "sysemu/kvm.h"
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#include "trace.h"
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void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis)
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{
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spapr->irq_map_nr = nr_msis;
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spapr->irq_map = bitmap_new(spapr->irq_map_nr);
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}
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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Error **errp)
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{
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int irq;
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/*
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* The 'align_mask' parameter of bitmap_find_next_zero_area()
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* should be one less than a power of 2; 0 means no
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* alignment. Adapt the 'align' value of the former allocator
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* to fit the requirements of bitmap_find_next_zero_area()
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*/
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align -= 1;
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irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
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align);
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if (irq == spapr->irq_map_nr) {
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error_setg(errp, "can't find a free %d-IRQ block", num);
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return -1;
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}
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bitmap_set(spapr->irq_map, irq, num);
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return irq + SPAPR_IRQ_MSI;
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}
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num)
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{
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bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
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}
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void spapr_irq_msi_reset(SpaprMachineState *spapr)
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{
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bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
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}
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static void spapr_irq_init_device(SpaprMachineState *spapr,
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SpaprIrq *irq, Error **errp)
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{
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MachineState *machine = MACHINE(spapr);
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Error *local_err = NULL;
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if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
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irq->init_kvm(spapr, &local_err);
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if (local_err && machine_kernel_irqchip_required(machine)) {
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error_prepend(&local_err,
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"kernel_irqchip requested but unavailable: ");
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error_propagate(errp, local_err);
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return;
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}
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if (!local_err) {
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return;
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}
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/*
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* We failed to initialize the KVM device, fallback to
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* emulated mode
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*/
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error_prepend(&local_err, "kernel_irqchip allowed but unavailable: ");
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warn_report_err(local_err);
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}
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irq->init_emu(spapr, errp);
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}
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/*
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* XICS IRQ backend.
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*/
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static void spapr_irq_init_xics(SpaprMachineState *spapr, int nr_irqs,
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Error **errp)
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{
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Object *obj;
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Error *local_err = NULL;
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spapr_irq_init_device(spapr, &spapr_irq_xics, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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obj = object_new(TYPE_ICS_SIMPLE);
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object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
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object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
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&error_fatal);
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object_property_set_int(obj, nr_irqs, "nr-irqs", &error_fatal);
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object_property_set_bool(obj, true, "realized", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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spapr->ics = ICS_BASE(obj);
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}
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#define ICS_IRQ_FREE(ics, srcno) \
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(!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
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static int spapr_irq_claim_xics(SpaprMachineState *spapr, int irq, bool lsi,
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Error **errp)
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{
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ICSState *ics = spapr->ics;
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assert(ics);
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if (!ics_valid_irq(ics, irq)) {
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error_setg(errp, "IRQ %d is invalid", irq);
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return -1;
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}
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if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
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error_setg(errp, "IRQ %d is not free", irq);
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return -1;
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}
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ics_set_irq_type(ics, irq - ics->offset, lsi);
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return 0;
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}
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static void spapr_irq_free_xics(SpaprMachineState *spapr, int irq, int num)
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{
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ICSState *ics = spapr->ics;
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uint32_t srcno = irq - ics->offset;
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int i;
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if (ics_valid_irq(ics, irq)) {
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trace_spapr_irq_free(0, irq, num);
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for (i = srcno; i < srcno + num; ++i) {
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if (ICS_IRQ_FREE(ics, i)) {
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trace_spapr_irq_free_warn(0, i);
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}
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memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
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}
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}
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}
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static qemu_irq spapr_qirq_xics(SpaprMachineState *spapr, int irq)
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{
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ICSState *ics = spapr->ics;
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uint32_t srcno = irq - ics->offset;
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if (ics_valid_irq(ics, irq)) {
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return spapr->qirqs[srcno];
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}
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return NULL;
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}
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static void spapr_irq_print_info_xics(SpaprMachineState *spapr, Monitor *mon)
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{
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
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}
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ics_pic_print_info(spapr->ics, mon);
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}
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static void spapr_irq_cpu_intc_create_xics(SpaprMachineState *spapr,
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PowerPCCPU *cpu, Error **errp)
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{
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Error *local_err = NULL;
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Object *obj;
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SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
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obj = icp_create(OBJECT(cpu), TYPE_ICP, XICS_FABRIC(spapr),
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&local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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spapr_cpu->icp = ICP(obj);
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}
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static int spapr_irq_post_load_xics(SpaprMachineState *spapr, int version_id)
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{
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if (!kvm_irqchip_in_kernel()) {
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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icp_resend(spapr_cpu_state(cpu)->icp);
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}
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}
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return 0;
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}
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static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val)
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{
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SpaprMachineState *spapr = opaque;
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ics_simple_set_irq(spapr->ics, srcno, val);
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}
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static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp)
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{
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/* TODO: create the KVM XICS device */
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}
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static const char *spapr_irq_get_nodename_xics(SpaprMachineState *spapr)
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{
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return XICS_NODENAME;
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}
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static void spapr_irq_init_emu_xics(SpaprMachineState *spapr, Error **errp)
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{
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xics_spapr_init(spapr);
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}
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static void spapr_irq_init_kvm_xics(SpaprMachineState *spapr, Error **errp)
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{
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if (kvm_enabled()) {
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xics_kvm_init(spapr, errp);
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}
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}
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#define SPAPR_IRQ_XICS_NR_IRQS 0x1000
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#define SPAPR_IRQ_XICS_NR_MSIS \
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(XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
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SpaprIrq spapr_irq_xics = {
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.nr_irqs = SPAPR_IRQ_XICS_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XICS_NR_MSIS,
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.ov5 = SPAPR_OV5_XIVE_LEGACY,
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.init = spapr_irq_init_xics,
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.claim = spapr_irq_claim_xics,
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.free = spapr_irq_free_xics,
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.qirq = spapr_qirq_xics,
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.print_info = spapr_irq_print_info_xics,
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.dt_populate = spapr_dt_xics,
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.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
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.post_load = spapr_irq_post_load_xics,
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.reset = spapr_irq_reset_xics,
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.set_irq = spapr_irq_set_irq_xics,
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.get_nodename = spapr_irq_get_nodename_xics,
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.init_emu = spapr_irq_init_emu_xics,
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.init_kvm = spapr_irq_init_kvm_xics,
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};
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/*
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* XIVE IRQ backend.
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*/
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static void spapr_irq_init_xive(SpaprMachineState *spapr, int nr_irqs,
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Error **errp)
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{
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uint32_t nr_servers = spapr_max_server_number(spapr);
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DeviceState *dev;
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int i;
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Error *local_err = NULL;
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dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
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qdev_prop_set_uint32(dev, "nr-irqs", nr_irqs);
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/*
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* 8 XIVE END structures per CPU. One for each available priority
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*/
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qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
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qdev_init_nofail(dev);
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spapr->xive = SPAPR_XIVE(dev);
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/* Enable the CPU IPIs */
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for (i = 0; i < nr_servers; ++i) {
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spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
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}
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spapr_xive_hcall_init(spapr);
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spapr_irq_init_device(spapr, &spapr_irq_xive, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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static int spapr_irq_claim_xive(SpaprMachineState *spapr, int irq, bool lsi,
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Error **errp)
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{
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if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
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error_setg(errp, "IRQ %d is invalid", irq);
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return -1;
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}
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return 0;
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}
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static void spapr_irq_free_xive(SpaprMachineState *spapr, int irq, int num)
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{
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int i;
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for (i = irq; i < irq + num; ++i) {
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spapr_xive_irq_free(spapr->xive, i);
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}
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}
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static qemu_irq spapr_qirq_xive(SpaprMachineState *spapr, int irq)
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{
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SpaprXive *xive = spapr->xive;
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if (irq >= xive->nr_irqs) {
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return NULL;
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}
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/* The sPAPR machine/device should have claimed the IRQ before */
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assert(xive_eas_is_valid(&xive->eat[irq]));
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return spapr->qirqs[irq];
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}
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static void spapr_irq_print_info_xive(SpaprMachineState *spapr,
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Monitor *mon)
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{
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
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}
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spapr_xive_pic_print_info(spapr->xive, mon);
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}
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static void spapr_irq_cpu_intc_create_xive(SpaprMachineState *spapr,
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PowerPCCPU *cpu, Error **errp)
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{
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Error *local_err = NULL;
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Object *obj;
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SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
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obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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spapr_cpu->tctx = XIVE_TCTX(obj);
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/*
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* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
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* don't beneficiate from the reset of the XIVE IRQ backend
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*/
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spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
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}
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static int spapr_irq_post_load_xive(SpaprMachineState *spapr, int version_id)
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{
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return spapr_xive_post_load(spapr->xive, version_id);
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}
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static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp)
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{
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CPUState *cs;
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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/* (TCG) Set the OS CAM line of the thread interrupt context. */
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spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
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}
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/* Activate the XIVE MMIOs */
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spapr_xive_mmio_set_enabled(spapr->xive, true);
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}
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static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val)
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{
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SpaprMachineState *spapr = opaque;
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if (kvm_irqchip_in_kernel()) {
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kvmppc_xive_source_set_irq(&spapr->xive->source, srcno, val);
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} else {
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xive_source_set_irq(&spapr->xive->source, srcno, val);
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}
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}
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static const char *spapr_irq_get_nodename_xive(SpaprMachineState *spapr)
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{
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return spapr->xive->nodename;
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}
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static void spapr_irq_init_emu_xive(SpaprMachineState *spapr, Error **errp)
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{
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spapr_xive_init(spapr->xive, errp);
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}
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static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp)
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{
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if (kvm_enabled()) {
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kvmppc_xive_connect(spapr->xive, errp);
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}
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}
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/*
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* XIVE uses the full IRQ number space. Set it to 8K to be compatible
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* with XICS.
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*/
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#define SPAPR_IRQ_XIVE_NR_IRQS 0x2000
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#define SPAPR_IRQ_XIVE_NR_MSIS (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
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SpaprIrq spapr_irq_xive = {
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.nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XIVE_NR_MSIS,
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.ov5 = SPAPR_OV5_XIVE_EXPLOIT,
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.init = spapr_irq_init_xive,
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.claim = spapr_irq_claim_xive,
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.free = spapr_irq_free_xive,
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.qirq = spapr_qirq_xive,
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.print_info = spapr_irq_print_info_xive,
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.dt_populate = spapr_dt_xive,
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.cpu_intc_create = spapr_irq_cpu_intc_create_xive,
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.post_load = spapr_irq_post_load_xive,
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.reset = spapr_irq_reset_xive,
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.set_irq = spapr_irq_set_irq_xive,
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.get_nodename = spapr_irq_get_nodename_xive,
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.init_emu = spapr_irq_init_emu_xive,
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.init_kvm = spapr_irq_init_kvm_xive,
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};
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/*
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* Dual XIVE and XICS IRQ backend.
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*
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* Both interrupt mode, XIVE and XICS, objects are created but the
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* machine starts in legacy interrupt mode (XICS). It can be changed
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* by the CAS negotiation process and, in that case, the new mode is
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* activated after an extra machine reset.
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*/
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/*
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* Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
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* default.
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*/
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static SpaprIrq *spapr_irq_current(SpaprMachineState *spapr)
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{
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return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ?
|
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&spapr_irq_xive : &spapr_irq_xics;
|
|
}
|
|
|
|
static void spapr_irq_init_dual(SpaprMachineState *spapr, int nr_irqs,
|
|
Error **errp)
|
|
{
|
|
MachineState *machine = MACHINE(spapr);
|
|
Error *local_err = NULL;
|
|
|
|
if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
|
|
error_setg(errp, "No KVM support for the 'dual' machine");
|
|
return;
|
|
}
|
|
|
|
spapr_irq_xics.init(spapr, spapr_irq_xics.nr_irqs, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
spapr_irq_xive.init(spapr, spapr_irq_xive.nr_irqs, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static int spapr_irq_claim_dual(SpaprMachineState *spapr, int irq, bool lsi,
|
|
Error **errp)
|
|
{
|
|
Error *local_err = NULL;
|
|
int ret;
|
|
|
|
ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return ret;
|
|
}
|
|
|
|
ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void spapr_irq_free_dual(SpaprMachineState *spapr, int irq, int num)
|
|
{
|
|
spapr_irq_xics.free(spapr, irq, num);
|
|
spapr_irq_xive.free(spapr, irq, num);
|
|
}
|
|
|
|
static qemu_irq spapr_qirq_dual(SpaprMachineState *spapr, int irq)
|
|
{
|
|
return spapr_irq_current(spapr)->qirq(spapr, irq);
|
|
}
|
|
|
|
static void spapr_irq_print_info_dual(SpaprMachineState *spapr, Monitor *mon)
|
|
{
|
|
spapr_irq_current(spapr)->print_info(spapr, mon);
|
|
}
|
|
|
|
static void spapr_irq_dt_populate_dual(SpaprMachineState *spapr,
|
|
uint32_t nr_servers, void *fdt,
|
|
uint32_t phandle)
|
|
{
|
|
spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle);
|
|
}
|
|
|
|
static void spapr_irq_cpu_intc_create_dual(SpaprMachineState *spapr,
|
|
PowerPCCPU *cpu, Error **errp)
|
|
{
|
|
Error *local_err = NULL;
|
|
|
|
spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
spapr_irq_xics.cpu_intc_create(spapr, cpu, errp);
|
|
}
|
|
|
|
static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int version_id)
|
|
{
|
|
/*
|
|
* Force a reset of the XIVE backend after migration. The machine
|
|
* defaults to XICS at startup.
|
|
*/
|
|
if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
|
|
spapr_irq_xive.reset(spapr, &error_fatal);
|
|
}
|
|
|
|
return spapr_irq_current(spapr)->post_load(spapr, version_id);
|
|
}
|
|
|
|
static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp)
|
|
{
|
|
/*
|
|
* Deactivate the XIVE MMIOs. The XIVE backend will reenable them
|
|
* if selected.
|
|
*/
|
|
spapr_xive_mmio_set_enabled(spapr->xive, false);
|
|
|
|
spapr_irq_current(spapr)->reset(spapr, errp);
|
|
}
|
|
|
|
static void spapr_irq_set_irq_dual(void *opaque, int srcno, int val)
|
|
{
|
|
SpaprMachineState *spapr = opaque;
|
|
|
|
spapr_irq_current(spapr)->set_irq(spapr, srcno, val);
|
|
}
|
|
|
|
static const char *spapr_irq_get_nodename_dual(SpaprMachineState *spapr)
|
|
{
|
|
return spapr_irq_current(spapr)->get_nodename(spapr);
|
|
}
|
|
|
|
/*
|
|
* Define values in sync with the XIVE and XICS backend
|
|
*/
|
|
#define SPAPR_IRQ_DUAL_NR_IRQS 0x2000
|
|
#define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
|
|
|
|
SpaprIrq spapr_irq_dual = {
|
|
.nr_irqs = SPAPR_IRQ_DUAL_NR_IRQS,
|
|
.nr_msis = SPAPR_IRQ_DUAL_NR_MSIS,
|
|
.ov5 = SPAPR_OV5_XIVE_BOTH,
|
|
|
|
.init = spapr_irq_init_dual,
|
|
.claim = spapr_irq_claim_dual,
|
|
.free = spapr_irq_free_dual,
|
|
.qirq = spapr_qirq_dual,
|
|
.print_info = spapr_irq_print_info_dual,
|
|
.dt_populate = spapr_irq_dt_populate_dual,
|
|
.cpu_intc_create = spapr_irq_cpu_intc_create_dual,
|
|
.post_load = spapr_irq_post_load_dual,
|
|
.reset = spapr_irq_reset_dual,
|
|
.set_irq = spapr_irq_set_irq_dual,
|
|
.get_nodename = spapr_irq_get_nodename_dual,
|
|
.init_emu = NULL, /* should not be used */
|
|
.init_kvm = NULL, /* should not be used */
|
|
};
|
|
|
|
|
|
static void spapr_irq_check(SpaprMachineState *spapr, Error **errp)
|
|
{
|
|
MachineState *machine = MACHINE(spapr);
|
|
|
|
/*
|
|
* Sanity checks on non-P9 machines. On these, XIVE is not
|
|
* advertised, see spapr_dt_ov5_platform_support()
|
|
*/
|
|
if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
|
|
0, spapr->max_compat_pvr)) {
|
|
/*
|
|
* If the 'dual' interrupt mode is selected, force XICS as CAS
|
|
* negotiation is useless.
|
|
*/
|
|
if (spapr->irq == &spapr_irq_dual) {
|
|
spapr->irq = &spapr_irq_xics;
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Non-P9 machines using only XIVE is a bogus setup. We have two
|
|
* scenarios to take into account because of the compat mode:
|
|
*
|
|
* 1. POWER7/8 machines should fail to init later on when creating
|
|
* the XIVE interrupt presenters because a POWER9 exception
|
|
* model is required.
|
|
|
|
* 2. POWER9 machines using the POWER8 compat mode won't fail and
|
|
* will let the OS boot with a partial XIVE setup : DT
|
|
* properties but no hcalls.
|
|
*
|
|
* To cover both and not confuse the OS, add an early failure in
|
|
* QEMU.
|
|
*/
|
|
if (spapr->irq == &spapr_irq_xive) {
|
|
error_setg(errp, "XIVE-only machines require a POWER9 CPU");
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* sPAPR IRQ frontend routines for devices
|
|
*/
|
|
void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
|
|
{
|
|
MachineState *machine = MACHINE(spapr);
|
|
Error *local_err = NULL;
|
|
|
|
if (machine_kernel_irqchip_split(machine)) {
|
|
error_setg(errp, "kernel_irqchip split mode not supported on pseries");
|
|
return;
|
|
}
|
|
|
|
if (!kvm_enabled() && machine_kernel_irqchip_required(machine)) {
|
|
error_setg(errp,
|
|
"kernel_irqchip requested but only available with KVM");
|
|
return;
|
|
}
|
|
|
|
spapr_irq_check(spapr, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
/* Initialize the MSI IRQ allocator. */
|
|
if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
|
|
spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
|
|
}
|
|
|
|
spapr->irq->init(spapr, spapr->irq->nr_irqs, errp);
|
|
|
|
spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
|
|
spapr->irq->nr_irqs);
|
|
}
|
|
|
|
int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp)
|
|
{
|
|
return spapr->irq->claim(spapr, irq, lsi, errp);
|
|
}
|
|
|
|
void spapr_irq_free(SpaprMachineState *spapr, int irq, int num)
|
|
{
|
|
spapr->irq->free(spapr, irq, num);
|
|
}
|
|
|
|
qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
|
|
{
|
|
return spapr->irq->qirq(spapr, irq);
|
|
}
|
|
|
|
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id)
|
|
{
|
|
return spapr->irq->post_load(spapr, version_id);
|
|
}
|
|
|
|
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp)
|
|
{
|
|
if (spapr->irq->reset) {
|
|
spapr->irq->reset(spapr, errp);
|
|
}
|
|
}
|
|
|
|
int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp)
|
|
{
|
|
const char *nodename = spapr->irq->get_nodename(spapr);
|
|
int offset, phandle;
|
|
|
|
offset = fdt_subnode_offset(fdt, 0, nodename);
|
|
if (offset < 0) {
|
|
error_setg(errp, "Can't find node \"%s\": %s", nodename,
|
|
fdt_strerror(offset));
|
|
return -1;
|
|
}
|
|
|
|
phandle = fdt_get_phandle(fdt, offset);
|
|
if (!phandle) {
|
|
error_setg(errp, "Can't get phandle of node \"%s\"", nodename);
|
|
return -1;
|
|
}
|
|
|
|
return phandle;
|
|
}
|
|
|
|
/*
|
|
* XICS legacy routines - to deprecate one day
|
|
*/
|
|
|
|
static int ics_find_free_block(ICSState *ics, int num, int alignnum)
|
|
{
|
|
int first, i;
|
|
|
|
for (first = 0; first < ics->nr_irqs; first += alignnum) {
|
|
if (num > (ics->nr_irqs - first)) {
|
|
return -1;
|
|
}
|
|
for (i = first; i < first + num; ++i) {
|
|
if (!ICS_IRQ_FREE(ics, i)) {
|
|
break;
|
|
}
|
|
}
|
|
if (i == (first + num)) {
|
|
return first;
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp)
|
|
{
|
|
ICSState *ics = spapr->ics;
|
|
int first = -1;
|
|
|
|
assert(ics);
|
|
|
|
/*
|
|
* MSIMesage::data is used for storing VIRQ so
|
|
* it has to be aligned to num to support multiple
|
|
* MSI vectors. MSI-X is not affected by this.
|
|
* The hint is used for the first IRQ, the rest should
|
|
* be allocated continuously.
|
|
*/
|
|
if (align) {
|
|
assert((num == 1) || (num == 2) || (num == 4) ||
|
|
(num == 8) || (num == 16) || (num == 32));
|
|
first = ics_find_free_block(ics, num, num);
|
|
} else {
|
|
first = ics_find_free_block(ics, num, 1);
|
|
}
|
|
|
|
if (first < 0) {
|
|
error_setg(errp, "can't find a free %d-IRQ block", num);
|
|
return -1;
|
|
}
|
|
|
|
return first + ics->offset;
|
|
}
|
|
|
|
#define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400
|
|
|
|
SpaprIrq spapr_irq_xics_legacy = {
|
|
.nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
|
|
.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
|
|
.ov5 = SPAPR_OV5_XIVE_LEGACY,
|
|
|
|
.init = spapr_irq_init_xics,
|
|
.claim = spapr_irq_claim_xics,
|
|
.free = spapr_irq_free_xics,
|
|
.qirq = spapr_qirq_xics,
|
|
.print_info = spapr_irq_print_info_xics,
|
|
.dt_populate = spapr_dt_xics,
|
|
.cpu_intc_create = spapr_irq_cpu_intc_create_xics,
|
|
.post_load = spapr_irq_post_load_xics,
|
|
.set_irq = spapr_irq_set_irq_xics,
|
|
.get_nodename = spapr_irq_get_nodename_xics,
|
|
};
|