allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
174 lines
4 KiB
C
174 lines
4 KiB
C
/*
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* CRIS helper routines.
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*
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* Copyright (c) 2007 AXIS Communications AB
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* Written by Edgar E. Iglesias.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdio.h>
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#include <string.h>
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#include "config.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "exec-all.h"
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{
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env->exception_index = -1;
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}
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int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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env->exception_index = 0xaa;
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env->debug1 = address;
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cpu_dump_state(env, stderr, fprintf, 0);
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printf("%s addr=%x env->pc=%x\n", __func__, address, env->pc);
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return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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{
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return addr;
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}
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#else /* !CONFIG_USER_ONLY */
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int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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struct cris_mmu_result_t res;
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int prot, miss;
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target_ulong phy;
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address &= TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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// printf ("%s pc=%x %x w=%d smmu=%d\n", __func__, env->pc, address, rw, is_softmmu);
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miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
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if (miss)
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{
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/* handle the miss. */
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phy = 0;
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env->exception_index = EXCP_MMU_MISS;
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}
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else
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{
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phy = res.phy;
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}
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// printf ("a=%x phy=%x\n", address, phy);
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return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
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}
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static void cris_shift_ccs(CPUState *env)
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{
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uint32_t ccs;
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/* Apply the ccs shift. */
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ccs = env->pregs[SR_CCS];
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ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);
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// printf ("ccs=%x %x\n", env->pregs[SR_CCS], ccs);
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env->pregs[SR_CCS] = ccs;
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}
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void do_interrupt(CPUState *env)
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{
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uint32_t ebp, isr;
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int irqnum;
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fflush(NULL);
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#if 0
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printf ("exception index=%d interrupt_req=%d\n",
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env->exception_index,
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env->interrupt_request);
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#endif
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switch (env->exception_index)
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{
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case EXCP_BREAK:
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// printf ("BREAK! %d\n", env->trapnr);
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irqnum = env->trapnr;
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ebp = env->pregs[SR_EBP];
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isr = ldl_code(ebp + irqnum * 4);
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env->pregs[SR_ERP] = env->pc + 2;
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env->pc = isr;
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cris_shift_ccs(env);
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break;
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case EXCP_MMU_MISS:
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// printf ("MMU miss\n");
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irqnum = 4;
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ebp = env->pregs[SR_EBP];
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isr = ldl_code(ebp + irqnum * 4);
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env->pregs[SR_ERP] = env->pc;
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env->pc = isr;
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cris_shift_ccs(env);
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break;
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default:
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{
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/* Maybe the irq was acked by sw before we got a
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change to take it. */
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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if (!env->pending_interrupts)
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return;
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if (!(env->pregs[SR_CCS] & I_FLAG)) {
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return;
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}
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irqnum = 31 -
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__builtin_clz(env->pending_interrupts);
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irqnum += 0x30;
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ebp = env->pregs[SR_EBP];
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isr = ldl_code(ebp + irqnum * 4);
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env->pregs[SR_ERP] = env->pc;
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env->pc = isr;
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cris_shift_ccs(env);
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#if 0
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printf ("%s ebp=%x %x isr=%x %d"
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" ir=%x pending=%x\n",
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__func__,
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ebp, ebp + irqnum * 4,
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isr, env->exception_index,
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env->interrupt_request,
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env->pending_interrupts);
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#endif
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}
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}
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break;
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}
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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{
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// printf ("%s\n", __func__);
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uint32_t phy = addr;
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struct cris_mmu_result_t res;
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int miss;
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miss = cris_mmu_translate(&res, env, addr, 0, 0);
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if (!miss)
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phy = res.phy;
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return phy;
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}
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#endif
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