The qos stuff belongs to qtest, so move it into that directory, too. Message-Id: <20191218103059.11729-8-thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
436 lines
14 KiB
C
436 lines
14 KiB
C
/*
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* libqos virtio PCI driver
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*
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* Copyright (c) 2014 Marc Marí
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/virtio.h"
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#include "libqos/virtio-pci.h"
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#include "libqos/pci.h"
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#include "libqos/pci-pc.h"
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#include "libqos/malloc.h"
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#include "libqos/malloc-pc.h"
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#include "libqos/qgraph.h"
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#include "standard-headers/linux/virtio_ring.h"
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#include "standard-headers/linux/virtio_pci.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_regs.h"
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#include "virtio-pci-modern.h"
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/* virtio-pci is a superclass of all virtio-xxx-pci devices;
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* the relation between virtio-pci and virtio-xxx-pci is implicit,
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* and therefore virtio-pci does not produce virtio and is not
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* reached by any edge, not even as a "contains" edge.
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* In facts, every device is a QVirtioPCIDevice with
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* additional fields, since every one has its own
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* number of queues and various attributes.
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* Virtio-pci provides default functions to start the
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* hw and destroy the object, and nodes that want to
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* override them should always remember to call the
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* original qvirtio_pci_destructor and qvirtio_pci_start_hw.
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*/
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#define CONFIG_BASE(dev) (VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))
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static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t off)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readb(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
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}
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/* PCI is always read in little-endian order
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* but virtio ( < 1.0) is in guest order
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* so with a big-endian guest the order has been reversed,
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* reverse it again
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* virtio-1.0 is always little-endian, like PCI
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*/
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static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t off)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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uint16_t value;
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value = qpci_io_readw(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
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if (qvirtio_is_big_endian(d)) {
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value = bswap16(value);
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}
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return value;
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}
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static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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uint32_t value;
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value = qpci_io_readl(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
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if (qvirtio_is_big_endian(d)) {
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value = bswap32(value);
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}
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return value;
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}
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static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t off)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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uint64_t val;
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val = qpci_io_readq(dev->pdev, dev->bar, CONFIG_BASE(dev) + off);
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if (qvirtio_is_big_endian(d)) {
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val = bswap64(val);
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}
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return val;
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}
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static uint64_t qvirtio_pci_get_features(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_HOST_FEATURES);
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}
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static void qvirtio_pci_set_features(QVirtioDevice *d, uint64_t features)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES, features);
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}
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static uint64_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES);
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}
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static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS);
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}
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static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS, status);
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}
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static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
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uint32_t data;
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if (dev->pdev->msix_enabled) {
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g_assert_cmpint(vqpci->msix_entry, !=, -1);
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if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
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/* No ISR checking should be done if masked, but read anyway */
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return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
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} else {
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data = qtest_readl(dev->pdev->bus->qts, vqpci->msix_addr);
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if (data == vqpci->msix_data) {
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qtest_writel(dev->pdev->bus->qts, vqpci->msix_addr, 0);
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return true;
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} else {
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return false;
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}
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}
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} else {
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return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1;
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}
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}
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static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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uint32_t data;
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if (dev->pdev->msix_enabled) {
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g_assert_cmpint(dev->config_msix_entry, !=, -1);
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if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
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/* No ISR checking should be done if masked, but read anyway */
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return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
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} else {
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data = qtest_readl(dev->pdev->bus->qts, dev->config_msix_addr);
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if (data == dev->config_msix_data) {
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qtest_writel(dev->pdev->bus->qts, dev->config_msix_addr, 0);
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return true;
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} else {
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return false;
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}
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}
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} else {
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return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 2;
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}
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}
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static void qvirtio_pci_wait_config_isr_status(QVirtioDevice *d,
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gint64 timeout_us)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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gint64 start_time = g_get_monotonic_time();
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do {
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g_assert(g_get_monotonic_time() - start_time <= timeout_us);
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qtest_clock_step(dev->pdev->bus->qts, 100);
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} while (!qvirtio_pci_get_config_isr_status(d));
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}
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static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_SEL, index);
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}
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static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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return qpci_io_readw(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NUM);
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}
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static void qvirtio_pci_set_queue_address(QVirtioDevice *d, QVirtQueue *vq)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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uint64_t pfn = vq->desc / VIRTIO_PCI_VRING_ALIGN;
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qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_PFN, pfn);
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}
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QVirtQueue *qvirtio_pci_virtqueue_setup_common(QVirtioDevice *d,
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QGuestAllocator *alloc,
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uint16_t index)
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{
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uint64_t feat;
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uint64_t addr;
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QVirtQueuePCI *vqpci;
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QVirtioPCIDevice *qvpcidev = container_of(d, QVirtioPCIDevice, vdev);
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vqpci = g_malloc0(sizeof(*vqpci));
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feat = d->bus->get_guest_features(d);
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d->bus->queue_select(d, index);
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vqpci->vq.vdev = d;
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vqpci->vq.index = index;
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vqpci->vq.size = d->bus->get_queue_size(d);
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vqpci->vq.free_head = 0;
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vqpci->vq.num_free = vqpci->vq.size;
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vqpci->vq.align = VIRTIO_PCI_VRING_ALIGN;
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vqpci->vq.indirect = feat & (1ull << VIRTIO_RING_F_INDIRECT_DESC);
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vqpci->vq.event = feat & (1ull << VIRTIO_RING_F_EVENT_IDX);
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vqpci->msix_entry = -1;
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vqpci->msix_addr = 0;
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vqpci->msix_data = 0x12345678;
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/* Check different than 0 */
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g_assert_cmpint(vqpci->vq.size, !=, 0);
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/* Check power of 2 */
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g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
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addr = guest_alloc(alloc, qvring_size(vqpci->vq.size,
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VIRTIO_PCI_VRING_ALIGN));
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qvring_init(qvpcidev->pdev->bus->qts, alloc, &vqpci->vq, addr);
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d->bus->set_queue_address(d, &vqpci->vq);
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return &vqpci->vq;
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}
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void qvirtio_pci_virtqueue_cleanup_common(QVirtQueue *vq,
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QGuestAllocator *alloc)
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{
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QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
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guest_free(alloc, vq->desc);
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g_free(vqpci);
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}
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static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
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{
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QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
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qpci_io_writew(dev->pdev, dev->bar, VIRTIO_PCI_QUEUE_NOTIFY, vq->index);
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}
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static const QVirtioBus qvirtio_pci_legacy = {
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.config_readb = qvirtio_pci_config_readb,
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.config_readw = qvirtio_pci_config_readw,
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.config_readl = qvirtio_pci_config_readl,
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.config_readq = qvirtio_pci_config_readq,
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.get_features = qvirtio_pci_get_features,
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.set_features = qvirtio_pci_set_features,
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.get_guest_features = qvirtio_pci_get_guest_features,
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.get_status = qvirtio_pci_get_status,
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.set_status = qvirtio_pci_set_status,
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.get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
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.wait_config_isr_status = qvirtio_pci_wait_config_isr_status,
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.queue_select = qvirtio_pci_queue_select,
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.get_queue_size = qvirtio_pci_get_queue_size,
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.set_queue_address = qvirtio_pci_set_queue_address,
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.virtqueue_setup = qvirtio_pci_virtqueue_setup_common,
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.virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup_common,
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.virtqueue_kick = qvirtio_pci_virtqueue_kick,
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};
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static void qvirtio_pci_set_config_vector(QVirtioPCIDevice *d, uint16_t entry)
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{
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uint16_t vector;
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qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR, entry);
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vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_CONFIG_VECTOR);
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g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
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}
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static void qvirtio_pci_set_queue_vector(QVirtioPCIDevice *d, uint16_t vq_idx,
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uint16_t entry)
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{
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uint16_t vector;
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qvirtio_pci_queue_select(&d->vdev, vq_idx);
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qpci_io_writew(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR, entry);
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vector = qpci_io_readw(d->pdev, d->bar, VIRTIO_MSI_QUEUE_VECTOR);
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g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
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}
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static const QVirtioPCIMSIXOps qvirtio_pci_msix_ops_legacy = {
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.set_config_vector = qvirtio_pci_set_config_vector,
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.set_queue_vector = qvirtio_pci_set_queue_vector,
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};
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void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
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{
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qpci_device_enable(d->pdev);
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d->bar = qpci_iomap(d->pdev, d->bar_idx, NULL);
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}
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void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
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{
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qpci_iounmap(d->pdev, d->bar);
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}
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void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
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QGuestAllocator *alloc, uint16_t entry)
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{
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uint32_t control;
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uint64_t off;
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g_assert(d->pdev->msix_enabled);
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off = d->pdev->msix_table_off + (entry * 16);
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g_assert_cmpint(entry, >=, 0);
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g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
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vqpci->msix_entry = entry;
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vqpci->msix_addr = guest_alloc(alloc, 4);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0UL);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_UPPER_ADDR,
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(vqpci->msix_addr >> 32) & ~0UL);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
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control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_VECTOR_CTRL);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_VECTOR_CTRL,
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control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
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d->msix_ops->set_queue_vector(d, vqpci->vq.index, entry);
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}
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void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
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QGuestAllocator *alloc, uint16_t entry)
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{
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uint32_t control;
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uint64_t off;
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g_assert(d->pdev->msix_enabled);
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off = d->pdev->msix_table_off + (entry * 16);
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g_assert_cmpint(entry, >=, 0);
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g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
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d->config_msix_entry = entry;
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d->config_msix_data = 0x12345678;
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d->config_msix_addr = guest_alloc(alloc, 4);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & ~0UL);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_UPPER_ADDR,
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(d->config_msix_addr >> 32) & ~0UL);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
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control = qpci_io_readl(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_VECTOR_CTRL);
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qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
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off + PCI_MSIX_ENTRY_VECTOR_CTRL,
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control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
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d->msix_ops->set_config_vector(d, entry);
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}
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void qvirtio_pci_destructor(QOSGraphObject *obj)
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{
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QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
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qvirtio_pci_device_disable(dev);
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g_free(dev->pdev);
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}
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void qvirtio_pci_start_hw(QOSGraphObject *obj)
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{
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QVirtioPCIDevice *dev = (QVirtioPCIDevice *)obj;
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qvirtio_pci_device_enable(dev);
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qvirtio_start_device(&dev->vdev);
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}
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static void qvirtio_pci_init_legacy(QVirtioPCIDevice *dev)
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{
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dev->vdev.device_type = qpci_config_readw(dev->pdev, PCI_SUBSYSTEM_ID);
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dev->bar_idx = 0;
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dev->vdev.bus = &qvirtio_pci_legacy;
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dev->msix_ops = &qvirtio_pci_msix_ops_legacy;
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dev->vdev.big_endian = qtest_big_endian(dev->pdev->bus->qts);
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}
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static void qvirtio_pci_init_from_pcidev(QVirtioPCIDevice *dev, QPCIDevice *pci_dev)
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{
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dev->pdev = pci_dev;
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dev->config_msix_entry = -1;
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if (!qvirtio_pci_init_virtio_1(dev)) {
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qvirtio_pci_init_legacy(dev);
|
|
}
|
|
|
|
/* each virtio-xxx-pci device should override at least this function */
|
|
dev->obj.get_driver = NULL;
|
|
dev->obj.start_hw = qvirtio_pci_start_hw;
|
|
dev->obj.destructor = qvirtio_pci_destructor;
|
|
}
|
|
|
|
void virtio_pci_init(QVirtioPCIDevice *dev, QPCIBus *bus, QPCIAddress * addr)
|
|
{
|
|
QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
|
|
g_assert_nonnull(pci_dev);
|
|
qvirtio_pci_init_from_pcidev(dev, pci_dev);
|
|
}
|
|
|
|
QVirtioPCIDevice *virtio_pci_new(QPCIBus *bus, QPCIAddress * addr)
|
|
{
|
|
QVirtioPCIDevice *dev;
|
|
QPCIDevice *pci_dev = qpci_device_find(bus, addr->devfn);
|
|
if (!pci_dev) {
|
|
return NULL;
|
|
}
|
|
|
|
dev = g_new0(QVirtioPCIDevice, 1);
|
|
qvirtio_pci_init_from_pcidev(dev, pci_dev);
|
|
dev->obj.free = g_free;
|
|
return dev;
|
|
}
|