Signed-off-by: Laurent Vivier <Laurent@vivier.eu> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6676 c046a42c-6fe2-441c-8c8c-71466251a162
846 lines
21 KiB
C
846 lines
21 KiB
C
/*
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* PowerMac descriptor-based DMA emulation
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*
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* Copyright (c) 2005-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2009 Laurent Vivier
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*
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* some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
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*
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* Definitions for using the Apple Descriptor-Based DMA controller
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* in Power Macintosh computers.
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*
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* Copyright (C) 1996 Paul Mackerras.
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*
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* some parts from mol 0.9.71
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*
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* Descriptor based DMA emulation
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*
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* Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "isa.h"
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#include "mac_dbdma.h"
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/* debug DBDMA */
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//#define DEBUG_DBDMA
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#ifdef DEBUG_DBDMA
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#define DBDMA_DPRINTF(fmt, args...) \
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do { printf("DBDMA: " fmt , ##args); } while (0)
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#else
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#define DBDMA_DPRINTF(fmt, args...)
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#endif
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/*
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*/
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/*
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* DBDMA control/status registers. All little-endian.
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*/
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#define DBDMA_CONTROL 0x00
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#define DBDMA_STATUS 0x01
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#define DBDMA_CMDPTR_HI 0x02
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#define DBDMA_CMDPTR_LO 0x03
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#define DBDMA_INTR_SEL 0x04
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#define DBDMA_BRANCH_SEL 0x05
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#define DBDMA_WAIT_SEL 0x06
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#define DBDMA_XFER_MODE 0x07
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#define DBDMA_DATA2PTR_HI 0x08
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#define DBDMA_DATA2PTR_LO 0x09
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#define DBDMA_RES1 0x0A
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#define DBDMA_ADDRESS_HI 0x0B
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#define DBDMA_BRANCH_ADDR_HI 0x0C
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#define DBDMA_RES2 0x0D
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#define DBDMA_RES3 0x0E
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#define DBDMA_RES4 0x0F
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#define DBDMA_REGS 16
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#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
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#define DBDMA_CHANNEL_SHIFT 7
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#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
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#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
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/* Bits in control and status registers */
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#define RUN 0x8000
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#define PAUSE 0x4000
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#define FLUSH 0x2000
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#define WAKE 0x1000
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#define DEAD 0x0800
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#define ACTIVE 0x0400
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#define BT 0x0100
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#define DEVSTAT 0x00ff
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/*
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* DBDMA command structure. These fields are all little-endian!
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*/
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typedef struct dbdma_cmd {
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uint16_t req_count; /* requested byte transfer count */
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uint16_t command; /* command word (has bit-fields) */
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uint32_t phy_addr; /* physical data address */
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uint32_t cmd_dep; /* command-dependent field */
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uint16_t res_count; /* residual count after completion */
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uint16_t xfer_status; /* transfer status */
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} dbdma_cmd;
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/* DBDMA command values in command field */
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#define COMMAND_MASK 0xf000
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#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
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#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
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#define INPUT_MORE 0x2000 /* transfer stream data to memory */
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#define INPUT_LAST 0x3000 /* ditto, expect end marker */
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#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
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#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
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#define DBDMA_NOP 0x6000 /* do nothing */
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#define DBDMA_STOP 0x7000 /* suspend processing */
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/* Key values in command field */
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#define KEY_MASK 0x0700
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#define KEY_STREAM0 0x0000 /* usual data stream */
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#define KEY_STREAM1 0x0100 /* control/status stream */
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#define KEY_STREAM2 0x0200 /* device-dependent stream */
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#define KEY_STREAM3 0x0300 /* device-dependent stream */
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#define KEY_STREAM4 0x0400 /* reserved */
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#define KEY_REGS 0x0500 /* device register space */
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#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
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#define KEY_DEVICE 0x0700 /* device memory-mapped space */
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/* Interrupt control values in command field */
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#define INTR_MASK 0x0030
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#define INTR_NEVER 0x0000 /* don't interrupt */
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#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
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#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
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#define INTR_ALWAYS 0x0030 /* always interrupt */
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/* Branch control values in command field */
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#define BR_MASK 0x000c
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#define BR_NEVER 0x0000 /* don't branch */
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#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
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#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
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#define BR_ALWAYS 0x000c /* always branch */
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/* Wait control values in command field */
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#define WAIT_MASK 0x0003
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#define WAIT_NEVER 0x0000 /* don't wait */
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#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
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#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
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#define WAIT_ALWAYS 0x0003 /* always wait */
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typedef struct DBDMA_channel {
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int channel;
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uint32_t regs[DBDMA_REGS];
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qemu_irq irq;
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DBDMA_io io;
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DBDMA_rw rw;
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dbdma_cmd current;
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int processing;
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} DBDMA_channel;
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#ifdef DEBUG_DBDMA
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static void dump_dbdma_cmd(dbdma_cmd *cmd)
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{
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printf("dbdma_cmd %p\n", cmd);
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printf(" req_count 0x%04x\n", le16_to_cpu(cmd->req_count));
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printf(" command 0x%04x\n", le16_to_cpu(cmd->command));
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printf(" phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr));
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printf(" cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep));
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printf(" res_count 0x%04x\n", le16_to_cpu(cmd->res_count));
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printf(" xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status));
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}
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#else
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static void dump_dbdma_cmd(dbdma_cmd *cmd)
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{
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}
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#endif
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static void dbdma_cmdptr_load(DBDMA_channel *ch)
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{
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DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
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be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
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cpu_physical_memory_read(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
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(uint8_t*)&ch->current, sizeof(dbdma_cmd));
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}
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static void dbdma_cmdptr_save(DBDMA_channel *ch)
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{
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DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
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be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
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DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
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le16_to_cpu(ch->current.xfer_status),
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le16_to_cpu(ch->current.res_count));
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cpu_physical_memory_write(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
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(uint8_t*)&ch->current, sizeof(dbdma_cmd));
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}
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static void kill_channel(DBDMA_channel *ch)
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{
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DBDMA_DPRINTF("kill_channel\n");
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ch->regs[DBDMA_STATUS] |= cpu_to_be32(DEAD);
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~ACTIVE);
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qemu_irq_raise(ch->irq);
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}
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static void conditional_interrupt(DBDMA_channel *ch)
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{
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dbdma_cmd *current = &ch->current;
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uint16_t intr;
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uint16_t sel_mask, sel_value;
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uint32_t status;
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int cond;
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DBDMA_DPRINTF("conditional_interrupt\n");
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intr = le16_to_cpu(current->command) & INTR_MASK;
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switch(intr) {
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case INTR_NEVER: /* don't interrupt */
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return;
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case INTR_ALWAYS: /* always interrupt */
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qemu_irq_raise(ch->irq);
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return;
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}
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status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;
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sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;
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cond = (status & sel_mask) == (sel_value & sel_mask);
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switch(intr) {
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case INTR_IFSET: /* intr if condition bit is 1 */
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if (cond)
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qemu_irq_raise(ch->irq);
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return;
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case INTR_IFCLR: /* intr if condition bit is 0 */
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if (!cond)
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qemu_irq_raise(ch->irq);
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return;
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}
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}
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static int conditional_wait(DBDMA_channel *ch)
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{
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dbdma_cmd *current = &ch->current;
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uint16_t wait;
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uint16_t sel_mask, sel_value;
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uint32_t status;
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int cond;
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DBDMA_DPRINTF("conditional_wait\n");
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wait = le16_to_cpu(current->command) & WAIT_MASK;
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switch(wait) {
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case WAIT_NEVER: /* don't wait */
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return 0;
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case WAIT_ALWAYS: /* always wait */
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return 1;
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}
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status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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sel_mask = (be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) >> 16) & 0x0f;
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sel_value = be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) & 0x0f;
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cond = (status & sel_mask) == (sel_value & sel_mask);
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switch(wait) {
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case WAIT_IFSET: /* wait if condition bit is 1 */
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if (cond)
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return 1;
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return 0;
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case WAIT_IFCLR: /* wait if condition bit is 0 */
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if (!cond)
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return 1;
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return 0;
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}
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return 0;
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}
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static void next(DBDMA_channel *ch)
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{
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uint32_t cp;
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~BT);
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cp = be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]);
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ch->regs[DBDMA_CMDPTR_LO] = cpu_to_be32(cp + sizeof(dbdma_cmd));
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dbdma_cmdptr_load(ch);
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}
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static void branch(DBDMA_channel *ch)
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{
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dbdma_cmd *current = &ch->current;
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ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep;
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ch->regs[DBDMA_STATUS] |= cpu_to_be32(BT);
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dbdma_cmdptr_load(ch);
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}
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static void conditional_branch(DBDMA_channel *ch)
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{
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dbdma_cmd *current = &ch->current;
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uint16_t br;
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uint16_t sel_mask, sel_value;
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uint32_t status;
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int cond;
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DBDMA_DPRINTF("conditional_branch\n");
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/* check if we must branch */
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br = le16_to_cpu(current->command) & BR_MASK;
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switch(br) {
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case BR_NEVER: /* don't branch */
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next(ch);
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return;
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case BR_ALWAYS: /* always branch */
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branch(ch);
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return;
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}
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status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
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sel_mask = (be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) >> 16) & 0x0f;
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sel_value = be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) & 0x0f;
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cond = (status & sel_mask) == (sel_value & sel_mask);
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switch(br) {
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case BR_IFSET: /* branch if condition bit is 1 */
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if (cond)
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branch(ch);
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else
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next(ch);
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return;
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case BR_IFCLR: /* branch if condition bit is 0 */
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if (!cond)
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branch(ch);
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else
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next(ch);
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return;
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}
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}
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static QEMUBH *dbdma_bh;
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static void channel_run(DBDMA_channel *ch);
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static void dbdma_end(DBDMA_io *io)
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{
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DBDMA_channel *ch = io->channel;
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dbdma_cmd *current = &ch->current;
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if (conditional_wait(ch))
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goto wait;
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current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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current->res_count = cpu_to_le16(be32_to_cpu(io->len));
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dbdma_cmdptr_save(ch);
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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conditional_interrupt(ch);
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conditional_branch(ch);
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wait:
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ch->processing = 0;
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if ((ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN)) &&
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(ch->regs[DBDMA_STATUS] & cpu_to_be32(ACTIVE)))
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channel_run(ch);
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}
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static void start_output(DBDMA_channel *ch, int key, uint32_t addr,
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uint16_t req_count, int is_last)
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{
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DBDMA_DPRINTF("start_output\n");
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/* KEY_REGS, KEY_DEVICE and KEY_STREAM
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* are not implemented in the mac-io chip
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*/
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DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
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if (!addr || key > KEY_STREAM3) {
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kill_channel(ch);
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return;
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}
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ch->io.addr = addr;
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ch->io.len = req_count;
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ch->io.is_last = is_last;
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ch->io.dma_end = dbdma_end;
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ch->io.is_dma_out = 1;
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ch->processing = 1;
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ch->rw(&ch->io);
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}
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static void start_input(DBDMA_channel *ch, int key, uint32_t addr,
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uint16_t req_count, int is_last)
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{
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DBDMA_DPRINTF("start_input\n");
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/* KEY_REGS, KEY_DEVICE and KEY_STREAM
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* are not implemented in the mac-io chip
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*/
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if (!addr || key > KEY_STREAM3) {
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kill_channel(ch);
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return;
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}
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ch->io.addr = addr;
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ch->io.len = req_count;
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ch->io.is_last = is_last;
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ch->io.dma_end = dbdma_end;
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ch->io.is_dma_out = 0;
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ch->processing = 1;
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ch->rw(&ch->io);
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}
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static void load_word(DBDMA_channel *ch, int key, uint32_t addr,
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uint16_t len)
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{
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dbdma_cmd *current = &ch->current;
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uint32_t val;
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DBDMA_DPRINTF("load_word\n");
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/* only implements KEY_SYSTEM */
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if (key != KEY_SYSTEM) {
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printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
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kill_channel(ch);
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return;
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}
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cpu_physical_memory_read(addr, (uint8_t*)&val, len);
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if (len == 2)
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val = (val << 16) | (current->cmd_dep & 0x0000ffff);
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else if (len == 1)
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val = (val << 24) | (current->cmd_dep & 0x00ffffff);
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current->cmd_dep = val;
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if (conditional_wait(ch))
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goto wait;
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current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
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dbdma_cmdptr_save(ch);
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ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
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conditional_interrupt(ch);
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next(ch);
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wait:
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qemu_bh_schedule(dbdma_bh);
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}
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static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
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uint16_t len)
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{
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dbdma_cmd *current = &ch->current;
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uint32_t val;
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DBDMA_DPRINTF("store_word\n");
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/* only implements KEY_SYSTEM */
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if (key != KEY_SYSTEM) {
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printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
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kill_channel(ch);
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return;
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}
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val = current->cmd_dep;
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if (len == 2)
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val >>= 16;
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else if (len == 1)
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val >>= 24;
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cpu_physical_memory_write(addr, (uint8_t*)&val, len);
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if (conditional_wait(ch))
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goto wait;
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current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
|
|
dbdma_cmdptr_save(ch);
|
|
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
|
|
|
|
conditional_interrupt(ch);
|
|
next(ch);
|
|
|
|
wait:
|
|
qemu_bh_schedule(dbdma_bh);
|
|
}
|
|
|
|
static void nop(DBDMA_channel *ch)
|
|
{
|
|
dbdma_cmd *current = &ch->current;
|
|
|
|
if (conditional_wait(ch))
|
|
goto wait;
|
|
|
|
current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
|
|
dbdma_cmdptr_save(ch);
|
|
|
|
conditional_interrupt(ch);
|
|
conditional_branch(ch);
|
|
|
|
wait:
|
|
qemu_bh_schedule(dbdma_bh);
|
|
}
|
|
|
|
static void stop(DBDMA_channel *ch)
|
|
{
|
|
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD|FLUSH));
|
|
|
|
/* the stop command does not increment command pointer */
|
|
}
|
|
|
|
static void channel_run(DBDMA_channel *ch)
|
|
{
|
|
dbdma_cmd *current = &ch->current;
|
|
uint16_t cmd, key;
|
|
uint16_t req_count;
|
|
uint32_t phy_addr;
|
|
|
|
DBDMA_DPRINTF("channel_run\n");
|
|
dump_dbdma_cmd(current);
|
|
|
|
/* clear WAKE flag at command fetch */
|
|
|
|
ch->regs[DBDMA_STATUS] &= cpu_to_be32(~WAKE);
|
|
|
|
cmd = le16_to_cpu(current->command) & COMMAND_MASK;
|
|
|
|
switch (cmd) {
|
|
case DBDMA_NOP:
|
|
nop(ch);
|
|
return;
|
|
|
|
case DBDMA_STOP:
|
|
stop(ch);
|
|
return;
|
|
}
|
|
|
|
key = le16_to_cpu(current->command) & 0x0700;
|
|
req_count = le16_to_cpu(current->req_count);
|
|
phy_addr = le32_to_cpu(current->phy_addr);
|
|
|
|
if (key == KEY_STREAM4) {
|
|
printf("command %x, invalid key 4\n", cmd);
|
|
kill_channel(ch);
|
|
return;
|
|
}
|
|
|
|
switch (cmd) {
|
|
case OUTPUT_MORE:
|
|
start_output(ch, key, phy_addr, req_count, 0);
|
|
return;
|
|
|
|
case OUTPUT_LAST:
|
|
start_output(ch, key, phy_addr, req_count, 1);
|
|
return;
|
|
|
|
case INPUT_MORE:
|
|
start_input(ch, key, phy_addr, req_count, 0);
|
|
return;
|
|
|
|
case INPUT_LAST:
|
|
start_input(ch, key, phy_addr, req_count, 1);
|
|
return;
|
|
}
|
|
|
|
if (key < KEY_REGS) {
|
|
printf("command %x, invalid key %x\n", cmd, key);
|
|
key = KEY_SYSTEM;
|
|
}
|
|
|
|
/* for LOAD_WORD and STORE_WORD, req_count is on 3 bits
|
|
* and BRANCH is invalid
|
|
*/
|
|
|
|
req_count = req_count & 0x0007;
|
|
if (req_count & 0x4) {
|
|
req_count = 4;
|
|
phy_addr &= ~3;
|
|
} else if (req_count & 0x2) {
|
|
req_count = 2;
|
|
phy_addr &= ~1;
|
|
} else
|
|
req_count = 1;
|
|
|
|
switch (cmd) {
|
|
case LOAD_WORD:
|
|
load_word(ch, key, phy_addr, req_count);
|
|
return;
|
|
|
|
case STORE_WORD:
|
|
store_word(ch, key, phy_addr, req_count);
|
|
return;
|
|
}
|
|
}
|
|
|
|
static void DBDMA_run (DBDMA_channel *ch)
|
|
{
|
|
int channel;
|
|
|
|
for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
|
|
uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
|
|
if (!ch->processing && (status & RUN) && (status & ACTIVE))
|
|
channel_run(ch);
|
|
}
|
|
}
|
|
|
|
static void DBDMA_run_bh(void *opaque)
|
|
{
|
|
DBDMA_channel *ch = opaque;
|
|
|
|
DBDMA_DPRINTF("DBDMA_run_bh\n");
|
|
|
|
DBDMA_run(ch);
|
|
}
|
|
|
|
void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
|
|
DBDMA_rw rw,
|
|
void *opaque)
|
|
{
|
|
DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan;
|
|
|
|
DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
|
|
|
|
ch->irq = irq;
|
|
ch->channel = nchan;
|
|
ch->rw = rw;
|
|
ch->io.opaque = opaque;
|
|
ch->io.channel = ch;
|
|
}
|
|
|
|
void DBDMA_schedule(void)
|
|
{
|
|
CPUState *env = cpu_single_env;
|
|
if (env)
|
|
cpu_interrupt(env, CPU_INTERRUPT_EXIT);
|
|
}
|
|
|
|
static void
|
|
dbdma_control_write(DBDMA_channel *ch)
|
|
{
|
|
uint16_t mask, value;
|
|
uint32_t status;
|
|
|
|
mask = (be32_to_cpu(ch->regs[DBDMA_CONTROL]) >> 16) & 0xffff;
|
|
value = be32_to_cpu(ch->regs[DBDMA_CONTROL]) & 0xffff;
|
|
|
|
value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT);
|
|
|
|
status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
|
|
|
|
status = (value & mask) | (status & ~mask);
|
|
|
|
if (status & WAKE)
|
|
status |= ACTIVE;
|
|
if (status & RUN) {
|
|
status |= ACTIVE;
|
|
status &= ~DEAD;
|
|
}
|
|
if (status & PAUSE)
|
|
status &= ~ACTIVE;
|
|
if ((be32_to_cpu(ch->regs[DBDMA_STATUS]) & RUN) && !(status & RUN)) {
|
|
/* RUN is cleared */
|
|
status &= ~(ACTIVE|DEAD);
|
|
}
|
|
|
|
DBDMA_DPRINTF(" status 0x%08x\n", status);
|
|
|
|
ch->regs[DBDMA_STATUS] = cpu_to_be32(status);
|
|
|
|
if (status & ACTIVE)
|
|
qemu_bh_schedule(dbdma_bh);
|
|
}
|
|
|
|
static void dbdma_writel (void *opaque,
|
|
target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
|
DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
|
|
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
|
|
|
|
DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
|
|
DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
|
|
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
|
|
|
|
/* cmdptr cannot be modified if channel is RUN or ACTIVE */
|
|
|
|
if (reg == DBDMA_CMDPTR_LO &&
|
|
(ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE)))
|
|
return;
|
|
|
|
ch->regs[reg] = value;
|
|
|
|
switch(reg) {
|
|
case DBDMA_CONTROL:
|
|
dbdma_control_write(ch);
|
|
break;
|
|
case DBDMA_CMDPTR_LO:
|
|
/* 16-byte aligned */
|
|
ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf);
|
|
dbdma_cmdptr_load(ch);
|
|
break;
|
|
case DBDMA_STATUS:
|
|
case DBDMA_INTR_SEL:
|
|
case DBDMA_BRANCH_SEL:
|
|
case DBDMA_WAIT_SEL:
|
|
/* nothing to do */
|
|
break;
|
|
case DBDMA_XFER_MODE:
|
|
case DBDMA_CMDPTR_HI:
|
|
case DBDMA_DATA2PTR_HI:
|
|
case DBDMA_DATA2PTR_LO:
|
|
case DBDMA_ADDRESS_HI:
|
|
case DBDMA_BRANCH_ADDR_HI:
|
|
case DBDMA_RES1:
|
|
case DBDMA_RES2:
|
|
case DBDMA_RES3:
|
|
case DBDMA_RES4:
|
|
/* unused */
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
|
|
{
|
|
uint32_t value;
|
|
int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
|
DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
|
|
int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
|
|
|
|
value = ch->regs[reg];
|
|
|
|
DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value);
|
|
DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
|
|
(uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
|
|
|
|
switch(reg) {
|
|
case DBDMA_CONTROL:
|
|
value = 0;
|
|
break;
|
|
case DBDMA_STATUS:
|
|
case DBDMA_CMDPTR_LO:
|
|
case DBDMA_INTR_SEL:
|
|
case DBDMA_BRANCH_SEL:
|
|
case DBDMA_WAIT_SEL:
|
|
/* nothing to do */
|
|
break;
|
|
case DBDMA_XFER_MODE:
|
|
case DBDMA_CMDPTR_HI:
|
|
case DBDMA_DATA2PTR_HI:
|
|
case DBDMA_DATA2PTR_LO:
|
|
case DBDMA_ADDRESS_HI:
|
|
case DBDMA_BRANCH_ADDR_HI:
|
|
/* unused */
|
|
value = 0;
|
|
break;
|
|
case DBDMA_RES1:
|
|
case DBDMA_RES2:
|
|
case DBDMA_RES3:
|
|
case DBDMA_RES4:
|
|
/* reserved */
|
|
break;
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
static CPUWriteMemoryFunc *dbdma_write[] = {
|
|
NULL,
|
|
NULL,
|
|
dbdma_writel,
|
|
};
|
|
|
|
static CPUReadMemoryFunc *dbdma_read[] = {
|
|
NULL,
|
|
NULL,
|
|
dbdma_readl,
|
|
};
|
|
|
|
static void dbdma_save(QEMUFile *f, void *opaque)
|
|
{
|
|
DBDMA_channel *s = opaque;
|
|
unsigned int i, j;
|
|
|
|
for (i = 0; i < DBDMA_CHANNELS; i++)
|
|
for (j = 0; j < DBDMA_REGS; j++)
|
|
qemu_put_be32s(f, &s[i].regs[j]);
|
|
}
|
|
|
|
static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
DBDMA_channel *s = opaque;
|
|
unsigned int i, j;
|
|
|
|
if (version_id != 2)
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < DBDMA_CHANNELS; i++)
|
|
for (j = 0; j < DBDMA_REGS; j++)
|
|
qemu_get_be32s(f, &s[i].regs[j]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dbdma_reset(void *opaque)
|
|
{
|
|
DBDMA_channel *s = opaque;
|
|
int i;
|
|
|
|
for (i = 0; i < DBDMA_CHANNELS; i++)
|
|
memset(s[i].regs, 0, DBDMA_SIZE);
|
|
}
|
|
|
|
void* DBDMA_init (int *dbdma_mem_index)
|
|
{
|
|
DBDMA_channel *s;
|
|
|
|
s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
|
|
|
|
*dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
|
|
register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
|
|
qemu_register_reset(dbdma_reset, s);
|
|
dbdma_reset(s);
|
|
|
|
dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
|
|
|
|
return s;
|
|
}
|