This will simplify the definition of new SoCs, like the AST2600 which should use a different CPU and a different IRQ number layout. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
381 lines
13 KiB
C
381 lines
13 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Jeremy Kerr <jk@ozlabs.org>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/address-spaces.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/char/serial.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "net/net.h"
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#define ASPEED_SOC_UART_5_BASE 0x00184000
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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#define ASPEED_SOC_IOMEM_BASE 0x1E600000
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#define ASPEED_SOC_FMC_BASE 0x1E620000
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#define ASPEED_SOC_SPI_BASE 0x1E630000
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#define ASPEED_SOC_SPI2_BASE 0x1E631000
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#define ASPEED_SOC_VIC_BASE 0x1E6C0000
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#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
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#define ASPEED_SOC_SCU_BASE 0x1E6E2000
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#define ASPEED_SOC_SRAM_BASE 0x1E720000
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#define ASPEED_SOC_TIMER_BASE 0x1E782000
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#define ASPEED_SOC_WDT_BASE 0x1E785000
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#define ASPEED_SOC_I2C_BASE 0x1E78A000
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#define ASPEED_SOC_ETH1_BASE 0x1E660000
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#define ASPEED_SOC_ETH2_BASE 0x1E680000
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static const int aspeed_soc_ast2400_irqmap[] = {
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[ASPEED_UART1] = 9,
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[ASPEED_UART2] = 32,
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[ASPEED_UART3] = 33,
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[ASPEED_UART4] = 34,
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[ASPEED_UART5] = 10,
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[ASPEED_VUART] = 8,
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[ASPEED_FMC] = 19,
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[ASPEED_SDMC] = 0,
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[ASPEED_SCU] = 21,
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[ASPEED_ADC] = 31,
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[ASPEED_GPIO] = 20,
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[ASPEED_RTC] = 22,
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[ASPEED_TIMER1] = 16,
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[ASPEED_TIMER2] = 17,
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[ASPEED_TIMER3] = 18,
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[ASPEED_TIMER4] = 35,
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[ASPEED_TIMER5] = 36,
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[ASPEED_TIMER6] = 37,
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[ASPEED_TIMER7] = 38,
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[ASPEED_TIMER8] = 39,
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[ASPEED_WDT] = 27,
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[ASPEED_PWM] = 28,
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[ASPEED_LPC] = 8,
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[ASPEED_IBT] = 8, /* LPC */
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[ASPEED_I2C] = 12,
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[ASPEED_ETH1] = 2,
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[ASPEED_ETH2] = 3,
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};
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#define AST2400_SDRAM_BASE 0x40000000
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#define AST2500_SDRAM_BASE 0x80000000
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/* AST2500 uses the same IRQs as the AST2400 */
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#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
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static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
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static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
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static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
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ASPEED_SOC_SPI2_BASE};
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static const char *aspeed_soc_ast2500_typenames[] = {
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"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
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static const AspeedSoCInfo aspeed_socs[] = {
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{
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.name = "ast2400-a0",
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.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
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.silicon_rev = AST2400_A0_SILICON_REV,
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.sdram_base = AST2400_SDRAM_BASE,
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.sram_size = 0x8000,
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.spis_num = 1,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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.wdts_num = 2,
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.irqmap = aspeed_soc_ast2400_irqmap,
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}, {
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.name = "ast2400-a1",
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.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
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.silicon_rev = AST2400_A1_SILICON_REV,
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.sdram_base = AST2400_SDRAM_BASE,
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.sram_size = 0x8000,
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.spis_num = 1,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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.wdts_num = 2,
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.irqmap = aspeed_soc_ast2400_irqmap,
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}, {
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.name = "ast2400",
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.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
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.silicon_rev = AST2400_A0_SILICON_REV,
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.sdram_base = AST2400_SDRAM_BASE,
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.sram_size = 0x8000,
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.spis_num = 1,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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.wdts_num = 2,
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.irqmap = aspeed_soc_ast2400_irqmap,
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}, {
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.name = "ast2500-a1",
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.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
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.silicon_rev = AST2500_A1_SILICON_REV,
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.sdram_base = AST2500_SDRAM_BASE,
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.sram_size = 0x9000,
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.spis_num = 2,
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.spi_bases = aspeed_soc_ast2500_spi_bases,
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.fmc_typename = "aspeed.smc.ast2500-fmc",
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.spi_typename = aspeed_soc_ast2500_typenames,
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.wdts_num = 3,
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.irqmap = aspeed_soc_ast2500_irqmap,
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},
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};
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static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
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}
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static void aspeed_soc_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu),
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sc->info->cpu_type, &error_abort, NULL);
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sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
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TYPE_ASPEED_SCU);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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sc->info->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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"hw-strap1", &error_abort);
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
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"hw-strap2", &error_abort);
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object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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"hw-prot-key", &error_abort);
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sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
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TYPE_ASPEED_VIC);
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sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
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sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
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object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
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OBJECT(&s->scu), &error_abort);
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sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
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TYPE_ASPEED_I2C);
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sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
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sc->info->fmc_typename);
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object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
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&error_abort);
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for (i = 0; i < sc->info->spis_num; i++) {
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sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
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sizeof(s->spi[i]), sc->info->spi_typename[i]);
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}
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sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
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TYPE_ASPEED_SDMC);
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qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
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sc->info->silicon_rev);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size", &error_abort);
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object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
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"max-ram-size", &error_abort);
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for (i = 0; i < sc->info->wdts_num; i++) {
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sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
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sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
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qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
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sc->info->silicon_rev);
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}
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sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100),
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sizeof(s->ftgmac100), TYPE_FTGMAC100);
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}
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static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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{
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int i;
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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Error *err = NULL, *local_err = NULL;
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/* IO space */
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create_unimplemented_device("aspeed_soc.io",
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ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);
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/* CPU */
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object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* SRAM */
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memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
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sc->info->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
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&s->sram);
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/* SCU */
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object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
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/* VIC */
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
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/* Timer */
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object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
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for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
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qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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}
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/* UART - attach an 8250 to the IO space as our UART5 */
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if (serial_hd(0)) {
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qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
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serial_mm_init(get_system_memory(),
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ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
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uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
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}
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/* I2C */
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object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
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aspeed_soc_get_irq(s, ASPEED_I2C));
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/* FMC, The number of CS is set at the board level */
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object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
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s->fmc.ctrl->flash_window_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
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aspeed_soc_get_irq(s, ASPEED_FMC));
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/* SPI */
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for (i = 0; i < sc->info->spis_num; i++) {
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object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
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object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
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&local_err);
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error_propagate(&err, local_err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
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s->spi[i].ctrl->flash_window_base);
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}
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/* SDMC - SDRAM Memory Controller */
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object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
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/* Watch dog */
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for (i = 0; i < sc->info->wdts_num; i++) {
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object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
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ASPEED_SOC_WDT_BASE + i * 0x20);
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}
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/* Net */
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qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
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object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
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object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
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&local_err);
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error_propagate(&err, local_err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
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aspeed_soc_get_irq(s, ASPEED_ETH1));
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}
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static void aspeed_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
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sc->info = (AspeedSoCInfo *) data;
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dc->realize = aspeed_soc_realize;
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/* Reason: Uses serial_hds and nd_table in realize() directly */
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dc->user_creatable = false;
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}
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static const TypeInfo aspeed_soc_type_info = {
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.name = TYPE_ASPEED_SOC,
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.parent = TYPE_DEVICE,
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.instance_init = aspeed_soc_init,
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.instance_size = sizeof(AspeedSoCState),
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.class_size = sizeof(AspeedSoCClass),
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.abstract = true,
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};
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static void aspeed_soc_register_types(void)
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{
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int i;
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type_register_static(&aspeed_soc_type_info);
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for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
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TypeInfo ti = {
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.name = aspeed_socs[i].name,
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.parent = TYPE_ASPEED_SOC,
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.class_init = aspeed_soc_class_init,
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.class_data = (void *) &aspeed_socs[i],
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};
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type_register(&ti);
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}
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}
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type_init(aspeed_soc_register_types)
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