Since it can`t fail. Also modify the callers. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
872 lines
26 KiB
C
872 lines
26 KiB
C
/*
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* QEMU Ultrasparc APB PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2012,2013 Artyom Tarasenko
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* XXX This file and most of its contents are somewhat misnamed. The
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
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the secondary PCI bridge. */
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci-host/apb.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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/* debug APB */
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//#define DEBUG_APB
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#ifdef DEBUG_APB
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#define APB_DPRINTF(fmt, ...) \
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do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define APB_DPRINTF(fmt, ...)
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#endif
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/* debug IOMMU */
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//#define DEBUG_IOMMU
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#ifdef DEBUG_IOMMU
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#define IOMMU_DPRINTF(fmt, ...) \
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do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define IOMMU_DPRINTF(fmt, ...)
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#endif
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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* http://www.sun.com/processors/manuals/805-0087.pdf
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*
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* APB: "Advanced PCI Bridge (APB) User's Manual",
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* http://www.sun.com/processors/manuals/805-1251.pdf
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*/
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#define PBM_PCI_IMR_MASK 0x7fffffff
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#define PBM_PCI_IMR_ENABLED 0x80000000
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#define POR (1U << 31)
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#define SOFT_POR (1U << 30)
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#define SOFT_XIR (1U << 29)
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#define BTN_POR (1U << 28)
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#define BTN_XIR (1U << 27)
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#define RESET_MASK 0xf8000000
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#define RESET_WCMASK 0x98000000
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#define RESET_WMASK 0x60000000
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#define MAX_IVEC 0x40
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#define NO_IRQ_REQUEST (MAX_IVEC + 1)
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#define IOMMU_PAGE_SIZE_8K (1ULL << 13)
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#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
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#define IOMMU_PAGE_SIZE_64K (1ULL << 16)
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#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
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#define IOMMU_NREGS 3
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#define IOMMU_CTRL 0x0
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#define IOMMU_CTRL_TBW_SIZE (1ULL << 2)
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#define IOMMU_CTRL_MMU_EN (1ULL)
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#define IOMMU_CTRL_TSB_SHIFT 16
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#define IOMMU_BASE 0x8
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#define IOMMU_FLUSH 0x10
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#define IOMMU_TTE_DATA_V (1ULL << 63)
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#define IOMMU_TTE_DATA_SIZE (1ULL << 61)
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#define IOMMU_TTE_DATA_W (1ULL << 1)
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#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
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#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL
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typedef struct IOMMUState {
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AddressSpace iommu_as;
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MemoryRegion iommu;
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uint64_t regs[IOMMU_NREGS];
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} IOMMUState;
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#define TYPE_APB "pbm"
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#define APB_DEVICE(obj) \
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OBJECT_CHECK(APBState, (obj), TYPE_APB)
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typedef struct APBState {
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PCIHostState parent_obj;
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MemoryRegion apb_config;
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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MemoryRegion pci_ioport;
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uint64_t pci_irq_in;
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IOMMUState iommu;
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t pci_err_irq_map[4];
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uint32_t obio_irq_map[32];
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qemu_irq *pbm_irqs;
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qemu_irq *ivec_irqs;
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unsigned int irq_request;
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uint32_t reset_control;
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unsigned int nr_resets;
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} APBState;
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static inline void pbm_set_request(APBState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
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s->irq_request = irq_num;
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qemu_set_irq(s->ivec_irqs[irq_num], 1);
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}
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static inline void pbm_check_irqs(APBState *s)
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{
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unsigned int i;
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/* Previous request is not acknowledged, resubmit */
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if (s->irq_request != NO_IRQ_REQUEST) {
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pbm_set_request(s, s->irq_request);
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return;
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}
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/* no request pending */
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if (s->pci_irq_in == 0ULL) {
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return;
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}
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for (i = 0; i < 32; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, i);
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return;
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}
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}
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}
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for (i = 32; i < 64; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
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pbm_set_request(s, i);
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break;
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}
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}
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}
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}
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static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
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{
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APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
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qemu_set_irq(s->ivec_irqs[irq_num], 0);
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s->irq_request = NO_IRQ_REQUEST;
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}
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static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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{
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IOMMUState *is = opaque;
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return &is->iommu_as;
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}
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/* Called from RCU critical section */
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static IOMMUTLBEntry pbm_translate_iommu(MemoryRegion *iommu, hwaddr addr,
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bool is_write)
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{
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IOMMUState *is = container_of(iommu, IOMMUState, iommu);
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hwaddr baseaddr, offset;
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uint64_t tte;
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uint32_t tsbsize;
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IOMMUTLBEntry ret = {
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.target_as = &address_space_memory,
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.iova = 0,
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.translated_addr = 0,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
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/* IOMMU disabled, passthrough using standard 8K page */
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ret.iova = addr & IOMMU_PAGE_MASK_8K;
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ret.translated_addr = addr;
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ret.addr_mask = IOMMU_PAGE_MASK_8K;
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ret.perm = IOMMU_RW;
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return ret;
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}
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baseaddr = is->regs[IOMMU_BASE >> 3];
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tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
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if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
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/* 64K */
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switch (tsbsize) {
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case 0:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
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break;
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case 1:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
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break;
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case 2:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
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break;
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case 3:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
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break;
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case 4:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
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break;
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case 5:
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offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
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break;
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default:
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/* Not implemented, error */
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return ret;
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}
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} else {
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/* 8K */
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switch (tsbsize) {
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case 0:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
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break;
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case 1:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
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break;
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case 2:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
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break;
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case 3:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
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break;
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case 4:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
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break;
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case 5:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
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break;
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case 6:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
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break;
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case 7:
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offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
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break;
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}
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}
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tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
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MEMTXATTRS_UNSPECIFIED, NULL);
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if (!(tte & IOMMU_TTE_DATA_V)) {
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/* Invalid mapping */
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return ret;
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}
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if (tte & IOMMU_TTE_DATA_W) {
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/* Writeable */
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ret.perm = IOMMU_RW;
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} else {
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ret.perm = IOMMU_RO;
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}
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/* Extract phys */
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if (tte & IOMMU_TTE_DATA_SIZE) {
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/* 64K */
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ret.iova = addr & IOMMU_PAGE_MASK_64K;
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ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
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ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
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} else {
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/* 8K */
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ret.iova = addr & IOMMU_PAGE_MASK_8K;
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ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
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ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
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}
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return ret;
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}
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static MemoryRegionIOMMUOps pbm_iommu_ops = {
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.translate = pbm_translate_iommu,
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};
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static void iommu_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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IOMMUState *is = opaque;
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IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64
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" size: %d\n", addr, val, size);
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switch (addr) {
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case IOMMU_CTRL:
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if (size == 4) {
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is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
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is->regs[IOMMU_CTRL >> 3] |= val << 32;
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} else {
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is->regs[IOMMU_CTRL >> 3] = val;
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}
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break;
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case IOMMU_CTRL + 0x4:
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is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
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is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
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break;
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case IOMMU_BASE:
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if (size == 4) {
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is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
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is->regs[IOMMU_BASE >> 3] |= val << 32;
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} else {
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is->regs[IOMMU_BASE >> 3] = val;
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}
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break;
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case IOMMU_BASE + 0x4:
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is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
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is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
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break;
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case IOMMU_FLUSH:
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case IOMMU_FLUSH + 0x4:
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"apb iommu: Unimplemented register write "
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"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
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addr, size, val);
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break;
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}
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}
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static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size)
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{
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IOMMUState *is = opaque;
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uint64_t val;
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switch (addr) {
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case IOMMU_CTRL:
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if (size == 4) {
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val = is->regs[IOMMU_CTRL >> 3] >> 32;
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} else {
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val = is->regs[IOMMU_CTRL >> 3];
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}
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break;
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case IOMMU_CTRL + 0x4:
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val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
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break;
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case IOMMU_BASE:
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if (size == 4) {
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val = is->regs[IOMMU_BASE >> 3] >> 32;
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} else {
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val = is->regs[IOMMU_BASE >> 3];
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}
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break;
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case IOMMU_BASE + 0x4:
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val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
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break;
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case IOMMU_FLUSH:
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case IOMMU_FLUSH + 0x4:
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val = 0;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"apb iommu: Unimplemented register read "
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"reg 0x%" HWADDR_PRIx " size 0x%x\n",
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addr, size);
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val = 0;
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break;
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}
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IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64
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" size: %d\n", addr, val, size);
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return val;
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}
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static void apb_config_writel (void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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APBState *s = opaque;
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IOMMUState *is = &s->iommu;
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APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x217: /* IOMMU */
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iommu_config_write(is, (addr & 0x1f), val, size);
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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unsigned int ino = (addr & 0x3f) >> 3;
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s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
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pbm_clear_request(s, ino);
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}
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pbm_check_irqs(s);
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}
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break;
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case 0x1000 ... 0x107f: /* OBIO interrupt control */
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if (addr & 4) {
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unsigned int ino = ((addr & 0xff) >> 3);
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s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
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s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == (ino | 0x20))
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&& !(val & ~PBM_PCI_IMR_MASK)) {
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pbm_clear_request(s, ino | 0x20);
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}
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pbm_check_irqs(s);
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}
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break;
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case 0x1400 ... 0x14ff: /* PCI interrupt clear */
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if (addr & 4) {
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unsigned int ino = (addr & 0xff) >> 5;
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if ((s->irq_request / 4) == ino) {
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pbm_clear_request(s, s->irq_request);
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pbm_check_irqs(s);
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}
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}
|
|
break;
|
|
case 0x1800 ... 0x1860: /* OBIO interrupt clear */
|
|
if (addr & 4) {
|
|
unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
|
|
if (s->irq_request == ino) {
|
|
pbm_clear_request(s, ino);
|
|
pbm_check_irqs(s);
|
|
}
|
|
}
|
|
break;
|
|
case 0x2000 ... 0x202f: /* PCI control */
|
|
s->pci_control[(addr & 0x3f) >> 2] = val;
|
|
break;
|
|
case 0xf020 ... 0xf027: /* Reset control */
|
|
if (addr & 4) {
|
|
val &= RESET_MASK;
|
|
s->reset_control &= ~(val & RESET_WCMASK);
|
|
s->reset_control |= val & RESET_WMASK;
|
|
if (val & SOFT_POR) {
|
|
s->nr_resets = 0;
|
|
qemu_system_reset_request();
|
|
} else if (val & SOFT_XIR) {
|
|
qemu_system_reset_request();
|
|
}
|
|
}
|
|
break;
|
|
case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
|
|
case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
|
|
case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
|
|
case 0xf000 ... 0xf01f: /* FFB config, memory control */
|
|
/* we don't care */
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint64_t apb_config_readl (void *opaque,
|
|
hwaddr addr, unsigned size)
|
|
{
|
|
APBState *s = opaque;
|
|
IOMMUState *is = &s->iommu;
|
|
uint32_t val;
|
|
|
|
switch (addr & 0xffff) {
|
|
case 0x30 ... 0x4f: /* DMA error registers */
|
|
val = 0;
|
|
/* XXX: not implemented yet */
|
|
break;
|
|
case 0x200 ... 0x217: /* IOMMU */
|
|
val = iommu_config_read(is, (addr & 0x1f), size);
|
|
break;
|
|
case 0xc00 ... 0xc3f: /* PCI interrupt control */
|
|
if (addr & 4) {
|
|
val = s->pci_irq_map[(addr & 0x3f) >> 3];
|
|
} else {
|
|
val = 0;
|
|
}
|
|
break;
|
|
case 0x1000 ... 0x107f: /* OBIO interrupt control */
|
|
if (addr & 4) {
|
|
val = s->obio_irq_map[(addr & 0xff) >> 3];
|
|
} else {
|
|
val = 0;
|
|
}
|
|
break;
|
|
case 0x1080 ... 0x108f: /* PCI bus error */
|
|
if (addr & 4) {
|
|
val = s->pci_err_irq_map[(addr & 0xf) >> 3];
|
|
} else {
|
|
val = 0;
|
|
}
|
|
break;
|
|
case 0x2000 ... 0x202f: /* PCI control */
|
|
val = s->pci_control[(addr & 0x3f) >> 2];
|
|
break;
|
|
case 0xf020 ... 0xf027: /* Reset control */
|
|
if (addr & 4) {
|
|
val = s->reset_control;
|
|
} else {
|
|
val = 0;
|
|
}
|
|
break;
|
|
case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
|
|
case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
|
|
case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
|
|
case 0xf000 ... 0xf01f: /* FFB config, memory control */
|
|
/* we don't care */
|
|
default:
|
|
val = 0;
|
|
break;
|
|
}
|
|
APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
|
|
|
|
return val;
|
|
}
|
|
|
|
static const MemoryRegionOps apb_config_ops = {
|
|
.read = apb_config_readl,
|
|
.write = apb_config_writel,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void apb_pci_config_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned size)
|
|
{
|
|
APBState *s = opaque;
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
|
|
|
val = qemu_bswap_len(val, size);
|
|
APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
|
|
pci_data_write(phb->bus, addr, val, size);
|
|
}
|
|
|
|
static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
|
|
unsigned size)
|
|
{
|
|
uint32_t ret;
|
|
APBState *s = opaque;
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
|
|
|
ret = pci_data_read(phb->bus, addr, size);
|
|
ret = qemu_bswap_len(ret, size);
|
|
APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
|
|
return ret;
|
|
}
|
|
|
|
/* The APB host has an IRQ line for each IRQ line of each slot. */
|
|
static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
|
|
{
|
|
return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
|
|
}
|
|
|
|
static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
|
|
{
|
|
int bus_offset;
|
|
if (pci_dev->devfn & 1)
|
|
bus_offset = 16;
|
|
else
|
|
bus_offset = 0;
|
|
return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
|
|
}
|
|
|
|
static void pci_apb_set_irq(void *opaque, int irq_num, int level)
|
|
{
|
|
APBState *s = opaque;
|
|
|
|
APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
|
|
/* PCI IRQ map onto the first 32 INO. */
|
|
if (irq_num < 32) {
|
|
if (level) {
|
|
s->pci_irq_in |= 1ULL << irq_num;
|
|
if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
|
|
pbm_set_request(s, irq_num);
|
|
}
|
|
} else {
|
|
s->pci_irq_in &= ~(1ULL << irq_num);
|
|
}
|
|
} else {
|
|
/* OBIO IRQ map onto the next 32 INO. */
|
|
if (level) {
|
|
APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
|
|
s->pci_irq_in |= 1ULL << irq_num;
|
|
if ((s->irq_request == NO_IRQ_REQUEST)
|
|
&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
|
|
pbm_set_request(s, irq_num);
|
|
}
|
|
} else {
|
|
s->pci_irq_in &= ~(1ULL << irq_num);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int apb_pci_bridge_initfn(PCIDevice *dev)
|
|
{
|
|
pci_bridge_initfn(dev, TYPE_PCI_BUS);
|
|
|
|
/*
|
|
* command register:
|
|
* According to PCI bridge spec, after reset
|
|
* bus master bit is off
|
|
* memory space enable bit is off
|
|
* According to manual (805-1251.pdf).
|
|
* the reset value should be zero unless the boot pin is tied high
|
|
* (which is true) and thus it should be PCI_COMMAND_MEMORY.
|
|
*/
|
|
pci_set_word(dev->config + PCI_COMMAND,
|
|
PCI_COMMAND_MEMORY);
|
|
pci_set_word(dev->config + PCI_STATUS,
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
|
|
PCI_STATUS_DEVSEL_MEDIUM);
|
|
return 0;
|
|
}
|
|
|
|
PCIBus *pci_apb_init(hwaddr special_base,
|
|
hwaddr mem_base,
|
|
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
|
|
qemu_irq **pbm_irqs)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
PCIHostState *phb;
|
|
APBState *d;
|
|
IOMMUState *is;
|
|
PCIDevice *pci_dev;
|
|
PCIBridge *br;
|
|
|
|
/* Ultrasparc PBM main bus */
|
|
dev = qdev_create(NULL, TYPE_APB);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
/* apb_config */
|
|
sysbus_mmio_map(s, 0, special_base);
|
|
/* PCI configuration space */
|
|
sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
|
|
/* pci_ioport */
|
|
sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
|
|
d = APB_DEVICE(dev);
|
|
|
|
memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
|
|
memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
|
|
|
|
phb = PCI_HOST_BRIDGE(dev);
|
|
phb->bus = pci_register_bus(DEVICE(phb), "pci",
|
|
pci_apb_set_irq, pci_pbm_map_irq, d,
|
|
&d->pci_mmio,
|
|
get_system_io(),
|
|
0, 32, TYPE_PCI_BUS);
|
|
|
|
*pbm_irqs = d->pbm_irqs;
|
|
d->ivec_irqs = ivec_irqs;
|
|
|
|
pci_create_simple(phb->bus, 0, "pbm-pci");
|
|
|
|
/* APB IOMMU */
|
|
is = &d->iommu;
|
|
memset(is, 0, sizeof(IOMMUState));
|
|
|
|
memory_region_init_iommu(&is->iommu, OBJECT(dev), &pbm_iommu_ops,
|
|
"iommu-apb", UINT64_MAX);
|
|
address_space_init(&is->iommu_as, &is->iommu, "pbm-as");
|
|
pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
|
|
|
|
/* APB secondary busses */
|
|
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
|
|
"pbm-bridge");
|
|
br = PCI_BRIDGE(pci_dev);
|
|
pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
|
|
pci_apb_map_irq);
|
|
qdev_init_nofail(&pci_dev->qdev);
|
|
*bus2 = pci_bridge_get_sec_bus(br);
|
|
|
|
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
|
|
"pbm-bridge");
|
|
br = PCI_BRIDGE(pci_dev);
|
|
pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
|
|
pci_apb_map_irq);
|
|
qdev_init_nofail(&pci_dev->qdev);
|
|
*bus3 = pci_bridge_get_sec_bus(br);
|
|
|
|
return phb->bus;
|
|
}
|
|
|
|
static void pci_pbm_reset(DeviceState *d)
|
|
{
|
|
unsigned int i;
|
|
APBState *s = APB_DEVICE(d);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
|
|
}
|
|
for (i = 0; i < 32; i++) {
|
|
s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
|
|
}
|
|
|
|
s->irq_request = NO_IRQ_REQUEST;
|
|
s->pci_irq_in = 0ULL;
|
|
|
|
if (s->nr_resets++ == 0) {
|
|
/* Power on reset */
|
|
s->reset_control = POR;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps pci_config_ops = {
|
|
.read = apb_pci_config_read,
|
|
.write = apb_pci_config_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static int pci_pbm_init_device(SysBusDevice *dev)
|
|
{
|
|
APBState *s;
|
|
unsigned int i;
|
|
|
|
s = APB_DEVICE(dev);
|
|
for (i = 0; i < 8; i++) {
|
|
s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
|
|
}
|
|
for (i = 0; i < 2; i++) {
|
|
s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
|
|
}
|
|
for (i = 0; i < 32; i++) {
|
|
s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
|
|
}
|
|
s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
|
|
s->irq_request = NO_IRQ_REQUEST;
|
|
s->pci_irq_in = 0ULL;
|
|
|
|
/* apb_config */
|
|
memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
|
|
"apb-config", 0x10000);
|
|
/* at region 0 */
|
|
sysbus_init_mmio(dev, &s->apb_config);
|
|
|
|
memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
|
|
"apb-pci-config", 0x1000000);
|
|
/* at region 1 */
|
|
sysbus_init_mmio(dev, &s->pci_config);
|
|
|
|
/* pci_ioport */
|
|
memory_region_init_alias(&s->pci_ioport, OBJECT(s), "apb-pci-ioport",
|
|
get_system_io(), 0, 0x10000);
|
|
/* at region 2 */
|
|
sysbus_init_mmio(dev, &s->pci_ioport);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
|
|
{
|
|
pci_set_word(d->config + PCI_COMMAND,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
pci_set_word(d->config + PCI_STATUS,
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
|
|
PCI_STATUS_DEVSEL_MEDIUM);
|
|
}
|
|
|
|
static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
k->realize = pbm_pci_host_realize;
|
|
k->vendor_id = PCI_VENDOR_ID_SUN;
|
|
k->device_id = PCI_DEVICE_ID_SUN_SABRE;
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
|
/*
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
*/
|
|
dc->cannot_instantiate_with_device_add_yet = true;
|
|
}
|
|
|
|
static const TypeInfo pbm_pci_host_info = {
|
|
.name = "pbm-pci",
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PCIDevice),
|
|
.class_init = pbm_pci_host_class_init,
|
|
};
|
|
|
|
static void pbm_host_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = pci_pbm_init_device;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->reset = pci_pbm_reset;
|
|
}
|
|
|
|
static const TypeInfo pbm_host_info = {
|
|
.name = TYPE_APB,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(APBState),
|
|
.class_init = pbm_host_class_init,
|
|
};
|
|
|
|
static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->init = apb_pci_bridge_initfn;
|
|
k->exit = pci_bridge_exitfn;
|
|
k->vendor_id = PCI_VENDOR_ID_SUN;
|
|
k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
|
|
k->revision = 0x11;
|
|
k->config_write = pci_bridge_write_config;
|
|
k->is_bridge = 1;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->reset = pci_bridge_reset;
|
|
dc->vmsd = &vmstate_pci_device;
|
|
}
|
|
|
|
static const TypeInfo pbm_pci_bridge_info = {
|
|
.name = "pbm-bridge",
|
|
.parent = TYPE_PCI_BRIDGE,
|
|
.class_init = pbm_pci_bridge_class_init,
|
|
};
|
|
|
|
static void pbm_register_types(void)
|
|
{
|
|
type_register_static(&pbm_host_info);
|
|
type_register_static(&pbm_pci_host_info);
|
|
type_register_static(&pbm_pci_bridge_info);
|
|
}
|
|
|
|
type_init(pbm_register_types)
|