- TLB opcode group; - region protection option (ISA, 4.6.3); - region translation option (ISA, 4.6.4); - MMU option (ISA, 4.6.5). Cache control attribute bits are not used by this implementation. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
596 lines
18 KiB
C
596 lines
18 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu.h"
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#include "exec-all.h"
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#include "gdbstub.h"
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#include "qemu-common.h"
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#include "host-utils.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
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a1, a2, a3, a4, a5, a6) \
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{ .targno = (no), .type = (typ), .group = (grp) },
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static void reset_mmu(CPUState *env);
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void cpu_reset(CPUXtensaState *env)
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{
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env->exception_taken = 0;
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env->pc = env->config->exception_vector[EXC_RESET];
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env->sregs[LITBASE] &= ~1;
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env->sregs[PS] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
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env->sregs[VECBASE] = env->config->vecbase;
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env->pending_irq_level = 0;
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reset_mmu(env);
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}
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static const XtensaConfig core_config[] = {
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{
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.name = "sample-xtensa-core",
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.options = -1 ^
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(XTENSA_OPTION_BIT(XTENSA_OPTION_HW_ALIGNMENT) |
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XTENSA_OPTION_BIT(XTENSA_OPTION_MMU)),
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.gdb_regmap = {
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.num_regs = 176,
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.num_core_regs = 117,
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.reg = {
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#include "gdb-config-sample-xtensa-core.c"
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}
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},
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.nareg = 64,
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.ndepc = 1,
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.excm_level = 16,
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.vecbase = 0x5fff8400,
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.exception_vector = {
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[EXC_RESET] = 0x5fff8000,
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[EXC_WINDOW_OVERFLOW4] = 0x5fff8400,
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[EXC_WINDOW_UNDERFLOW4] = 0x5fff8440,
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[EXC_WINDOW_OVERFLOW8] = 0x5fff8480,
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[EXC_WINDOW_UNDERFLOW8] = 0x5fff84c0,
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[EXC_WINDOW_OVERFLOW12] = 0x5fff8500,
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[EXC_WINDOW_UNDERFLOW12] = 0x5fff8540,
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[EXC_KERNEL] = 0x5fff861c,
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[EXC_USER] = 0x5fff863c,
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[EXC_DOUBLE] = 0x5fff865c,
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},
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.ninterrupt = 13,
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.nlevel = 6,
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.interrupt_vector = {
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0,
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0,
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0x5fff857c,
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0x5fff859c,
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0x5fff85bc,
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0x5fff85dc,
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0x5fff85fc,
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},
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.level_mask = {
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[4] = 1,
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},
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.interrupt = {
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[0] = {
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.level = 4,
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.inttype = INTTYPE_TIMER,
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},
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},
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.nccompare = 1,
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.timerint = {
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[0] = 0,
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},
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.clock_freq_khz = 912000,
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},
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};
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CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
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{
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static int tcg_inited;
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CPUXtensaState *env;
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const XtensaConfig *config = NULL;
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int i;
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for (i = 0; i < ARRAY_SIZE(core_config); ++i)
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if (strcmp(core_config[i].name, cpu_model) == 0) {
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config = core_config + i;
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break;
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}
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if (config == NULL) {
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return NULL;
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}
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env = g_malloc0(sizeof(*env));
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env->config = config;
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cpu_exec_init(env);
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if (!tcg_inited) {
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tcg_inited = 1;
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xtensa_translate_init();
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}
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xtensa_irq_init(env);
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qemu_init_vcpu(env);
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return env;
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}
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void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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int i;
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cpu_fprintf(f, "Available CPUs:\n");
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for (i = 0; i < ARRAY_SIZE(core_config); ++i) {
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cpu_fprintf(f, " %s\n", core_config[i].name);
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}
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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uint32_t paddr;
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uint32_t page_size;
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unsigned access;
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if (xtensa_get_physical_addr(env, addr, 0, 0,
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&paddr, &page_size, &access) == 0) {
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return paddr;
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}
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if (xtensa_get_physical_addr(env, addr, 2, 0,
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&paddr, &page_size, &access) == 0) {
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return paddr;
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}
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return ~0;
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}
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static uint32_t relocated_vector(CPUState *env, uint32_t vector)
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{
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if (xtensa_option_enabled(env->config,
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XTENSA_OPTION_RELOCATABLE_VECTOR)) {
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return vector - env->config->vecbase + env->sregs[VECBASE];
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} else {
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return vector;
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}
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}
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/*!
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* Handle penging IRQ.
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* For the high priority interrupt jump to the corresponding interrupt vector.
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* For the level-1 interrupt convert it to either user, kernel or double
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* exception with the 'level-1 interrupt' exception cause.
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*/
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static void handle_interrupt(CPUState *env)
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{
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int level = env->pending_irq_level;
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if (level > xtensa_get_cintlevel(env) &&
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level <= env->config->nlevel &&
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(env->config->level_mask[level] &
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env->sregs[INTSET] &
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env->sregs[INTENABLE])) {
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if (level > 1) {
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env->sregs[EPC1 + level - 1] = env->pc;
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env->sregs[EPS2 + level - 2] = env->sregs[PS];
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env->sregs[PS] =
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(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
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env->pc = relocated_vector(env,
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env->config->interrupt_vector[level]);
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} else {
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env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
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if (env->sregs[PS] & PS_EXCM) {
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if (env->config->ndepc) {
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env->sregs[DEPC] = env->pc;
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} else {
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env->sregs[EPC1] = env->pc;
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}
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env->exception_index = EXC_DOUBLE;
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} else {
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env->sregs[EPC1] = env->pc;
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env->exception_index =
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(env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
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}
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env->sregs[PS] |= PS_EXCM;
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}
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env->exception_taken = 1;
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}
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}
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void do_interrupt(CPUState *env)
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{
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if (env->exception_index == EXC_IRQ) {
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qemu_log_mask(CPU_LOG_INT,
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"%s(EXC_IRQ) level = %d, cintlevel = %d, "
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"pc = %08x, a0 = %08x, ps = %08x, "
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"intset = %08x, intenable = %08x, "
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"ccount = %08x\n",
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__func__, env->pending_irq_level, xtensa_get_cintlevel(env),
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env->pc, env->regs[0], env->sregs[PS],
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env->sregs[INTSET], env->sregs[INTENABLE],
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env->sregs[CCOUNT]);
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handle_interrupt(env);
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}
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switch (env->exception_index) {
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case EXC_WINDOW_OVERFLOW4:
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case EXC_WINDOW_UNDERFLOW4:
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case EXC_WINDOW_OVERFLOW8:
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case EXC_WINDOW_UNDERFLOW8:
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case EXC_WINDOW_OVERFLOW12:
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case EXC_WINDOW_UNDERFLOW12:
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case EXC_KERNEL:
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case EXC_USER:
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case EXC_DOUBLE:
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qemu_log_mask(CPU_LOG_INT, "%s(%d) "
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"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
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__func__, env->exception_index,
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env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
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if (env->config->exception_vector[env->exception_index]) {
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env->pc = relocated_vector(env,
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env->config->exception_vector[env->exception_index]);
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env->exception_taken = 1;
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} else {
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qemu_log("%s(pc = %08x) bad exception_index: %d\n",
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__func__, env->pc, env->exception_index);
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}
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break;
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case EXC_IRQ:
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break;
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default:
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qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
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__func__, env->pc, env->exception_index);
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break;
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}
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check_interrupts(env);
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}
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static void reset_tlb_mmu_all_ways(CPUState *env,
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const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
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{
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unsigned wi, ei;
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for (wi = 0; wi < tlb->nways; ++wi) {
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for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
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entry[wi][ei].asid = 0;
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entry[wi][ei].variable = true;
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}
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}
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}
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static void reset_tlb_mmu_ways56(CPUState *env,
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const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
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{
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if (!tlb->varway56) {
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static const xtensa_tlb_entry way5[] = {
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{
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.vaddr = 0xd0000000,
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.paddr = 0,
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.asid = 1,
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.attr = 7,
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.variable = false,
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}, {
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.vaddr = 0xd8000000,
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.paddr = 0,
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.asid = 1,
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.attr = 3,
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.variable = false,
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}
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};
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static const xtensa_tlb_entry way6[] = {
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{
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.vaddr = 0xe0000000,
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.paddr = 0xf0000000,
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.asid = 1,
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.attr = 7,
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.variable = false,
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}, {
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.vaddr = 0xf0000000,
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.paddr = 0xf0000000,
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.asid = 1,
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.attr = 3,
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.variable = false,
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}
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};
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memcpy(entry[5], way5, sizeof(way5));
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memcpy(entry[6], way6, sizeof(way6));
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} else {
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uint32_t ei;
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for (ei = 0; ei < 8; ++ei) {
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entry[6][ei].vaddr = ei << 29;
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entry[6][ei].paddr = ei << 29;
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entry[6][ei].asid = 1;
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entry[6][ei].attr = 2;
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}
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}
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}
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static void reset_tlb_region_way0(CPUState *env,
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xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
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{
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unsigned ei;
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for (ei = 0; ei < 8; ++ei) {
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entry[0][ei].vaddr = ei << 29;
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entry[0][ei].paddr = ei << 29;
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entry[0][ei].asid = 1;
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entry[0][ei].attr = 2;
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entry[0][ei].variable = true;
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}
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}
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static void reset_mmu(CPUState *env)
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{
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
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env->sregs[RASID] = 0x04030201;
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env->sregs[ITLBCFG] = 0;
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env->sregs[DTLBCFG] = 0;
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env->autorefill_idx = 0;
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reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
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reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
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reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
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reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
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} else {
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reset_tlb_region_way0(env, env->itlb);
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reset_tlb_region_way0(env, env->dtlb);
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}
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}
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static unsigned get_ring(const CPUState *env, uint8_t asid)
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{
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unsigned i;
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for (i = 0; i < 4; ++i) {
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if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
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return i;
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}
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}
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return 0xff;
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}
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/*!
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* Lookup xtensa TLB for the given virtual address.
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* See ISA, 4.6.2.2
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*
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* \param pwi: [out] way index
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* \param pei: [out] entry index
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* \param pring: [out] access ring
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* \return 0 if ok, exception cause code otherwise
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*/
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int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb,
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uint32_t *pwi, uint32_t *pei, uint8_t *pring)
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{
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const xtensa_tlb *tlb = dtlb ?
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&env->config->dtlb : &env->config->itlb;
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const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
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env->dtlb : env->itlb;
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int nhits = 0;
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unsigned wi;
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for (wi = 0; wi < tlb->nways; ++wi) {
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uint32_t vpn;
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uint32_t ei;
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split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
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if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
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unsigned ring = get_ring(env, entry[wi][ei].asid);
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if (ring < 4) {
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if (++nhits > 1) {
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return dtlb ?
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LOAD_STORE_TLB_MULTI_HIT_CAUSE :
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INST_TLB_MULTI_HIT_CAUSE;
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}
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*pwi = wi;
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*pei = ei;
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*pring = ring;
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}
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}
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}
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return nhits ? 0 :
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(dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
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}
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/*!
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* Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
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* See ISA, 4.6.5.10
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*/
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static unsigned mmu_attr_to_access(uint32_t attr)
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{
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unsigned access = 0;
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if (attr < 12) {
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access |= PAGE_READ;
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if (attr & 0x1) {
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access |= PAGE_EXEC;
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}
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if (attr & 0x2) {
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access |= PAGE_WRITE;
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}
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} else if (attr == 13) {
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access |= PAGE_READ | PAGE_WRITE;
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}
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return access;
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}
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/*!
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* Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
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* See ISA, 4.6.3.3
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*/
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static unsigned region_attr_to_access(uint32_t attr)
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{
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unsigned access = 0;
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if ((attr < 6 && attr != 3) || attr == 14) {
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access |= PAGE_READ | PAGE_WRITE;
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}
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if (attr > 0 && attr < 6) {
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access |= PAGE_EXEC;
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}
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return access;
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}
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static bool is_access_granted(unsigned access, int is_write)
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{
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switch (is_write) {
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case 0:
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return access & PAGE_READ;
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case 1:
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return access & PAGE_WRITE;
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case 2:
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return access & PAGE_EXEC;
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default:
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return 0;
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}
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}
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static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
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uint32_t *wi, uint32_t *ei, uint8_t *ring);
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static int get_physical_addr_mmu(CPUState *env,
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uint32_t vaddr, int is_write, int mmu_idx,
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uint32_t *paddr, uint32_t *page_size, unsigned *access)
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{
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bool dtlb = is_write != 2;
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uint32_t wi;
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uint32_t ei;
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uint8_t ring;
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int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
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if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
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(mmu_idx != 0 || ((vaddr ^ env->sregs[PTEVADDR]) & 0xffc00000)) &&
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autorefill_mmu(env, vaddr, dtlb, &wi, &ei, &ring) == 0) {
|
|
ret = 0;
|
|
}
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
|
|
const xtensa_tlb_entry *entry =
|
|
xtensa_tlb_get_entry(env, dtlb, wi, ei);
|
|
|
|
if (ring < mmu_idx) {
|
|
return dtlb ?
|
|
LOAD_STORE_PRIVILEGE_CAUSE :
|
|
INST_FETCH_PRIVILEGE_CAUSE;
|
|
}
|
|
|
|
*access = mmu_attr_to_access(entry->attr);
|
|
if (!is_access_granted(*access, is_write)) {
|
|
return dtlb ?
|
|
(is_write ?
|
|
STORE_PROHIBITED_CAUSE :
|
|
LOAD_PROHIBITED_CAUSE) :
|
|
INST_FETCH_PROHIBITED_CAUSE;
|
|
}
|
|
|
|
*paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
|
|
*page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int autorefill_mmu(CPUState *env, uint32_t vaddr, bool dtlb,
|
|
uint32_t *wi, uint32_t *ei, uint8_t *ring)
|
|
{
|
|
uint32_t paddr;
|
|
uint32_t page_size;
|
|
unsigned access;
|
|
uint32_t pt_vaddr =
|
|
(env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
|
|
int ret = get_physical_addr_mmu(env, pt_vaddr, 0, 0,
|
|
&paddr, &page_size, &access);
|
|
|
|
qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
|
|
vaddr, ret ? ~0 : paddr);
|
|
|
|
if (ret == 0) {
|
|
uint32_t vpn;
|
|
uint32_t pte = ldl_phys(paddr);
|
|
|
|
*ring = (pte >> 4) & 0x3;
|
|
*wi = (++env->autorefill_idx) & 0x3;
|
|
split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei);
|
|
xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte);
|
|
qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
|
|
__func__, vaddr, vpn, pte);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int get_physical_addr_region(CPUState *env,
|
|
uint32_t vaddr, int is_write, int mmu_idx,
|
|
uint32_t *paddr, uint32_t *page_size, unsigned *access)
|
|
{
|
|
bool dtlb = is_write != 2;
|
|
uint32_t wi = 0;
|
|
uint32_t ei = (vaddr >> 29) & 0x7;
|
|
const xtensa_tlb_entry *entry =
|
|
xtensa_tlb_get_entry(env, dtlb, wi, ei);
|
|
|
|
*access = region_attr_to_access(entry->attr);
|
|
if (!is_access_granted(*access, is_write)) {
|
|
return dtlb ?
|
|
(is_write ?
|
|
STORE_PROHIBITED_CAUSE :
|
|
LOAD_PROHIBITED_CAUSE) :
|
|
INST_FETCH_PROHIBITED_CAUSE;
|
|
}
|
|
|
|
*paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
|
|
*page_size = ~REGION_PAGE_MASK + 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*!
|
|
* Convert virtual address to physical addr.
|
|
* MMU may issue pagewalk and change xtensa autorefill TLB way entry.
|
|
*
|
|
* \return 0 if ok, exception cause code otherwise
|
|
*/
|
|
int xtensa_get_physical_addr(CPUState *env,
|
|
uint32_t vaddr, int is_write, int mmu_idx,
|
|
uint32_t *paddr, uint32_t *page_size, unsigned *access)
|
|
{
|
|
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
|
|
return get_physical_addr_mmu(env, vaddr, is_write, mmu_idx,
|
|
paddr, page_size, access);
|
|
} else if (xtensa_option_bits_enabled(env->config,
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
|
|
XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
|
|
return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
|
|
paddr, page_size, access);
|
|
} else {
|
|
*paddr = vaddr;
|
|
*page_size = TARGET_PAGE_SIZE;
|
|
*access = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
|
return 0;
|
|
}
|
|
}
|