qemu-patch-raspberry4/target/ppc/translate
Stefan Brankovic b8313f0d91 target/ppc: Optimize emulation of vclzd instruction
Optimize Altivec instruction vclzd (Vector Count Leading Zeros Doubleword).
This instruction counts the number of leading zeros of each doubleword element
in source register and places result in the appropriate doubleword element of
destination register.

Using tcg-s count leading zeros instruction two times(once for each
doubleword element of source register vB) and placing result in
appropriate doubleword element of destination register vD.

Signed-off-by: Stefan Brankovic <stefan.brankovic@rt-rk.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1563200574-11098-6-git-send-email-stefan.brankovic@rt-rk.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-21 17:17:11 +10:00
..
dfp-impl.inc.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
dfp-ops.inc.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
fp-impl.inc.c target/ppc: Style fixes for translate/fp-impl.inc.c 2019-04-26 11:37:57 +10:00
fp-ops.inc.c target/ppc: add external PID support 2018-11-08 12:04:40 +11:00
spe-impl.inc.c target/ppc: Use tcg_gen_abs_i32 2019-05-13 22:52:08 +00:00
spe-ops.inc.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
vmx-impl.inc.c target/ppc: Optimize emulation of vclzd instruction 2019-08-21 17:17:11 +10:00
vmx-ops.inc.c Changes requirement for "vsubsbs" instruction 2018-12-21 09:29:12 +11:00
vsx-impl.inc.c target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro 2019-07-02 09:43:58 +10:00
vsx-ops.inc.c target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro 2019-07-02 09:43:58 +10:00