d944293d9a
The current EXRL tests crash on real machines: we must not use r0 as a base
register for trt/trtr, otherwise the content gets ignored. Also, we must
not use r0 for exrl, otherwise it gets ignored.
Let's use the "a" constraint so we get a general purpose register != r0.
For op2, we can simply specify a memory operand directly via "Q" (Memory
reference without index register and with short displacement).
Fixes: ad8c851d2e ("target/s390x: add EX support for TRT and TRTR")
Signed-off-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210111163845.18148-5-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
49 lines
1 KiB
C
49 lines
1 KiB
C
#include <stdint.h>
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#include <unistd.h>
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int main(void)
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{
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char op1[] = "hello";
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char op2[256];
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uint64_t r1 = 0xffffffffffffffffull;
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uint64_t r2 = 0xffffffffffffffffull;
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uint64_t cc;
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int i;
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for (i = 0; i < 256; i++) {
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if (i == 0) {
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op2[i] = 0xaa;
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} else {
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op2[i] = 0;
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}
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}
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asm volatile(
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" j 2f\n"
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"1: trt 0(1,%[op1]),%[op2]\n"
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"2: exrl %[op1_len],1b\n"
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" lgr %[r1],%%r1\n"
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" lgr %[r2],%%r2\n"
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" ipm %[cc]\n"
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: [r1] "+r" (r1),
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[r2] "+r" (r2),
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[cc] "=r" (cc)
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: [op1] "a" (&op1),
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[op1_len] "a" (5),
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[op2] "Q" (op2)
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: "r1", "r2", "cc");
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cc = (cc >> 28) & 3;
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if (cc != 2) {
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write(1, "bad cc\n", 7);
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return 1;
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}
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if ((char *)r1 != &op1[5]) {
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write(1, "bad r1\n", 7);
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return 1;
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}
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if (r2 != 0xffffffffffffffaaull) {
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write(1, "bad r2\n", 7);
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return 1;
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}
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return 0;
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}
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