Unify the duplicate code between get_hphys and mmu_translate, by simply making get_hphys call mmu_translate. This also fixes the support for 5-level nested page tables. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
472 lines
15 KiB
C
472 lines
15 KiB
C
/*
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* x86 exception helpers - sysemu code
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "tcg/helper-tcg.h"
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int get_pg_mode(CPUX86State *env)
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{
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int pg_mode = 0;
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if (env->cr[0] & CR0_WP_MASK) {
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pg_mode |= PG_MODE_WP;
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}
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if (env->cr[4] & CR4_PAE_MASK) {
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pg_mode |= PG_MODE_PAE;
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}
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if (env->cr[4] & CR4_PSE_MASK) {
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pg_mode |= PG_MODE_PSE;
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}
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if (env->cr[4] & CR4_PKE_MASK) {
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pg_mode |= PG_MODE_PKE;
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}
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if (env->cr[4] & CR4_PKS_MASK) {
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pg_mode |= PG_MODE_PKS;
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}
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if (env->cr[4] & CR4_SMEP_MASK) {
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pg_mode |= PG_MODE_SMEP;
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}
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if (env->cr[4] & CR4_LA57_MASK) {
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pg_mode |= PG_MODE_LA57;
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}
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if (env->hflags & HF_LMA_MASK) {
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pg_mode |= PG_MODE_LMA;
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}
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if (env->efer & MSR_EFER_NXE) {
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pg_mode |= PG_MODE_NXE;
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}
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return pg_mode;
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}
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#define PG_ERROR_OK (-1)
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typedef hwaddr (*MMUTranslateFunc)(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot);
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#define GET_HPHYS(cs, gpa, access_type, prot) \
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(get_hphys_func ? get_hphys_func(cs, gpa, access_type, prot) : gpa)
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static int mmu_translate(CPUState *cs, hwaddr addr, MMUTranslateFunc get_hphys_func,
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uint64_t cr3, int is_write1, int mmu_idx, int pg_mode,
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hwaddr *xlat, int *page_size, int *prot)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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uint64_t ptep, pte;
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int32_t a20_mask;
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target_ulong pde_addr, pte_addr;
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int error_code = 0;
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int is_dirty, is_write, is_user;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint32_t page_offset;
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uint32_t pkr;
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is_user = (mmu_idx == MMU_USER_IDX);
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is_write = is_write1 & 1;
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a20_mask = x86_get_a20_mask(env);
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if (!(pg_mode & PG_MODE_NXE)) {
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rsvd_mask |= PG_NX_MASK;
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}
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if (pg_mode & PG_MODE_PAE) {
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uint64_t pde, pdpe;
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target_ulong pdpe_addr;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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bool la57 = pg_mode & PG_MODE_LA57;
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uint64_t pml5e_addr, pml5e;
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uint64_t pml4e_addr, pml4e;
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int32_t sext;
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/* test virtual address sign extension */
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sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
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if (get_hphys_func && sext != 0 && sext != -1) {
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env->error_code = 0;
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cs->exception_index = EXCP0D_GPF;
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return 1;
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}
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if (la57) {
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pml5e_addr = ((cr3 & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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pml5e_addr = GET_HPHYS(cs, pml5e_addr, MMU_DATA_STORE, NULL);
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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if (!(pml5e & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml5e & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml5e & PG_ACCESSED_MASK)) {
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pml5e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml5e_addr, pml5e);
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}
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ptep = pml5e ^ PG_NX_MASK;
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} else {
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pml5e = cr3;
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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pml4e_addr = GET_HPHYS(cs, pml4e_addr, MMU_DATA_STORE, NULL);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml4e & PG_ACCESSED_MASK)) {
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pml4e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml4e_addr, pml4e);
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}
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
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a20_mask;
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pdpe_addr = GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pdpe & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pdpe ^ PG_NX_MASK;
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if (!(pdpe & PG_ACCESSED_MASK)) {
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pdpe |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pdpe_addr, pdpe);
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}
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if (pdpe & PG_PSE_MASK) {
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/* 1 GB page */
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*page_size = 1024 * 1024 * 1024;
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pte_addr = pdpe_addr;
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pte = pdpe;
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goto do_check_protect;
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}
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} else
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#endif
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{
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/* XXX: load them when cr3 is loaded ? */
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pdpe_addr = ((cr3 & ~0x1f) + ((addr >> 27) & 0x18)) &
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a20_mask;
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pdpe_addr = GET_HPHYS(cs, pdpe_addr, MMU_DATA_STORE, NULL);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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rsvd_mask |= PG_HI_USER_MASK;
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if (pdpe & (rsvd_mask | PG_NX_MASK)) {
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goto do_fault_rsvd;
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}
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
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a20_mask;
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pde_addr = GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL);
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pde & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pde ^ PG_NX_MASK;
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if (pde & PG_PSE_MASK) {
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/* 2 MB page */
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*page_size = 2048 * 1024;
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pte_addr = pde_addr;
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pte = pde;
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goto do_check_protect;
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}
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/* 4 KB page */
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
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a20_mask;
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pte_addr = GET_HPHYS(cs, pte_addr, MMU_DATA_STORE, NULL);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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/* combine pde and pte nx, user and rw protections */
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ptep &= pte ^ PG_NX_MASK;
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*page_size = 4096;
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} else {
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uint32_t pde;
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/* page directory entry */
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pde_addr = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) &
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a20_mask;
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pde_addr = GET_HPHYS(cs, pde_addr, MMU_DATA_STORE, NULL);
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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ptep = pde | PG_NX_MASK;
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/* if PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (pg_mode & PG_MODE_PSE)) {
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*page_size = 4096 * 1024;
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pte_addr = pde_addr;
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/* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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* Leave bits 20-13 in place for setting accessed/dirty bits below.
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*/
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pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
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rsvd_mask = 0x200000;
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goto do_check_protect_pse36;
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}
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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/* page directory entry */
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pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
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a20_mask;
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pte_addr = GET_HPHYS(cs, pte_addr, MMU_DATA_STORE, NULL);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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/* combine pde and pte user and rw protections */
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ptep &= pte | PG_NX_MASK;
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*page_size = 4096;
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rsvd_mask = 0;
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}
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do_check_protect:
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rsvd_mask |= (*page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
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do_check_protect_pse36:
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep ^= PG_NX_MASK;
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/* can the page can be put in the TLB? prot will tell us */
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if (is_user && !(ptep & PG_USER_MASK)) {
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goto do_fault_protect;
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}
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*prot = 0;
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if (mmu_idx != MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) {
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*prot |= PAGE_READ;
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if ((ptep & PG_RW_MASK) || !(is_user || (pg_mode & PG_MODE_WP))) {
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*prot |= PAGE_WRITE;
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}
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}
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if (!(ptep & PG_NX_MASK) &&
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(mmu_idx == MMU_USER_IDX ||
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!((pg_mode & PG_MODE_SMEP) && (ptep & PG_USER_MASK)))) {
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*prot |= PAGE_EXEC;
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}
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if (!(env->hflags & HF_LMA_MASK)) {
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pkr = 0;
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} else if (ptep & PG_USER_MASK) {
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pkr = pg_mode & PG_MODE_PKE ? env->pkru : 0;
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} else {
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pkr = pg_mode & PG_MODE_PKS ? env->pkrs : 0;
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}
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if (pkr) {
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uint32_t pk = (pte & PG_PKRU_MASK) >> PG_PKRU_BIT;
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uint32_t pkr_ad = (pkr >> pk * 2) & 1;
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uint32_t pkr_wd = (pkr >> pk * 2) & 2;
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uint32_t pkr_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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if (pkr_ad) {
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pkr_prot &= ~(PAGE_READ | PAGE_WRITE);
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} else if (pkr_wd && (is_user || (pg_mode & PG_MODE_WP))) {
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pkr_prot &= ~PAGE_WRITE;
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}
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*prot &= pkr_prot;
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if ((pkr_prot & (1 << is_write1)) == 0) {
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assert(is_write1 != 2);
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error_code |= PG_ERROR_PK_MASK;
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goto do_fault_protect;
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}
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}
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if ((*prot & (1 << is_write1)) == 0) {
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goto do_fault_protect;
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}
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/* yes, it can! */
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is_dirty = is_write && !(pte & PG_DIRTY_MASK);
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if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
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pte |= PG_ACCESSED_MASK;
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if (is_dirty) {
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pte |= PG_DIRTY_MASK;
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}
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x86_stl_phys_notdirty(cs, pte_addr, pte);
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}
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if (!(pte & PG_DIRTY_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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assert(!is_write);
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*prot &= ~PAGE_WRITE;
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}
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pte = pte & a20_mask;
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/* align to page_size */
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pte &= PG_ADDRESS_MASK & ~(*page_size - 1);
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page_offset = addr & (*page_size - 1);
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*xlat = GET_HPHYS(cs, pte + page_offset, is_write1, prot);
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return PG_ERROR_OK;
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do_fault_rsvd:
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error_code |= PG_ERROR_RSVD_MASK;
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do_fault_protect:
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error_code |= PG_ERROR_P_MASK;
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do_fault:
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error_code |= (is_write << PG_ERROR_W_BIT);
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if (is_user)
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error_code |= PG_ERROR_U_MASK;
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if (is_write1 == 2 &&
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(((pg_mode & PG_MODE_NXE) && (pg_mode & PG_MODE_PAE)) ||
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(pg_mode & PG_MODE_SMEP)))
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error_code |= PG_ERROR_I_D_MASK;
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return error_code;
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}
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static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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{
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CPUX86State *env = &X86_CPU(cs)->env;
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uint64_t exit_info_1;
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int page_size;
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int next_prot;
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hwaddr hphys;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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}
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exit_info_1 = mmu_translate(cs, gphys, NULL, env->nested_cr3,
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access_type, MMU_USER_IDX, env->nested_pg_mode,
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&hphys, &page_size, &next_prot);
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if (exit_info_1 == PG_ERROR_OK) {
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if (prot) {
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*prot &= next_prot;
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}
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return hphys;
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}
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x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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gphys);
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if (prot) {
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exit_info_1 |= SVM_NPTEXIT_GPA;
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} else { /* page table access */
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exit_info_1 |= SVM_NPTEXIT_GPT;
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}
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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/* return value:
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* -1 = cannot handle fault
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* 0 = nothing more to do
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* 1 = generate PF fault
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*/
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static int handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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int is_write1, int mmu_idx)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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int error_code = PG_ERROR_OK;
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int pg_mode, prot, page_size;
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hwaddr paddr;
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hwaddr vaddr;
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#if defined(DEBUG_MMU)
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printf("MMU fault: addr=%" VADDR_PRIx " w=%d mmu=%d eip=" TARGET_FMT_lx "\n",
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addr, is_write1, mmu_idx, env->eip);
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#endif
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if (!(env->cr[0] & CR0_PG_MASK)) {
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paddr = addr;
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#ifdef TARGET_X86_64
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if (!(env->hflags & HF_LMA_MASK)) {
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/* Without long mode we can only address 32bits in real mode */
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paddr = (uint32_t)paddr;
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}
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#endif
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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page_size = 4096;
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} else {
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pg_mode = get_pg_mode(env);
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error_code = mmu_translate(cs, addr, get_hphys, env->cr[3], is_write1,
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mmu_idx, pg_mode,
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&paddr, &page_size, &prot);
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}
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if (error_code == PG_ERROR_OK) {
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/* Even if 4MB pages, we map only one 4KB page in the cache to
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avoid filling it too fast */
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vaddr = addr & TARGET_PAGE_MASK;
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paddr &= TARGET_PAGE_MASK;
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assert(prot & (1 << is_write1));
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tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env),
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prot, mmu_idx, page_size);
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return 0;
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} else {
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if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
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/* cr2 is not modified in case of exceptions */
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x86_stq_phys(cs,
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env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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addr);
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} else {
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env->cr[2] = addr;
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}
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env->error_code = error_code;
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cs->exception_index = EXCP0E_PAGE;
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return 1;
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}
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}
|
|
|
|
bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
|
|
MMUAccessType access_type, int mmu_idx,
|
|
bool probe, uintptr_t retaddr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
env->retaddr = retaddr;
|
|
if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) {
|
|
/* FIXME: On error in get_hphys we have already jumped out. */
|
|
g_assert(!probe);
|
|
raise_exception_err_ra(env, cs->exception_index,
|
|
env->error_code, retaddr);
|
|
}
|
|
return true;
|
|
}
|