The we never allow i/o from user-only, and the tss check that helper_check_io does will always fail. Use an ifdef within gen_check_io and return false, indicating that an exception is known to be raised. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-50-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
155 lines
5.3 KiB
C
155 lines
5.3 KiB
C
/*
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* x86 segmentation related helpers: (sysemu-only code)
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* TSS, interrupts, system calls, jumps and call/task gates, descriptors
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "tcg/helper-tcg.h"
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#include "../seg_helper.h"
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#ifdef TARGET_X86_64
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void helper_syscall(CPUX86State *env, int next_eip_addend)
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{
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int selector;
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if (!(env->efer & MSR_EFER_SCE)) {
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raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
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}
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selector = (env->star >> 32) & 0xffff;
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if (env->hflags & HF_LMA_MASK) {
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int code64;
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env->regs[R_ECX] = env->eip + next_eip_addend;
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env->regs[11] = cpu_compute_eflags(env) & ~RF_MASK;
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code64 = env->hflags & HF_CS64_MASK;
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env->eflags &= ~(env->fmask | RF_MASK);
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cpu_load_eflags(env, env->eflags, 0);
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cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
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DESC_L_MASK);
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cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_W_MASK | DESC_A_MASK);
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if (code64) {
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env->eip = env->lstar;
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} else {
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env->eip = env->cstar;
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}
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} else {
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env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
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env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
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cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_W_MASK | DESC_A_MASK);
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env->eip = (uint32_t)env->star;
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}
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}
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#endif /* TARGET_X86_64 */
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void handle_even_inj(CPUX86State *env, int intno, int is_int,
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int error_code, int is_hw, int rm)
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{
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CPUState *cs = env_cpu(env);
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uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
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control.event_inj));
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if (!(event_inj & SVM_EVTINJ_VALID)) {
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int type;
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if (is_int) {
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type = SVM_EVTINJ_TYPE_SOFT;
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} else {
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type = SVM_EVTINJ_TYPE_EXEPT;
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}
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event_inj = intno | type | SVM_EVTINJ_VALID;
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if (!rm && exception_has_error_code(intno)) {
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event_inj |= SVM_EVTINJ_VALID_ERR;
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x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb,
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control.event_inj_err),
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error_code);
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}
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x86_stl_phys(cs,
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env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
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event_inj);
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}
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}
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void x86_cpu_do_interrupt(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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if (cs->exception_index == EXCP_VMEXIT) {
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assert(env->old_exception == -1);
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do_vmexit(env);
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} else {
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do_interrupt_all(cpu, cs->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip, 0);
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/* successfully delivered */
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env->old_exception = -1;
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}
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}
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/* check if Port I/O is allowed in TSS */
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void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size)
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{
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uintptr_t retaddr = GETPC();
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uint32_t io_offset, val, mask;
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/* TSS must be a valid 32 bit one */
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if (!(env->tr.flags & DESC_P_MASK) ||
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((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||
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env->tr.limit < 103) {
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goto fail;
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}
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io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr);
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io_offset += (addr >> 3);
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/* Note: the check needs two bytes */
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if ((io_offset + 1) > env->tr.limit) {
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goto fail;
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}
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val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr);
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val >>= (addr & 7);
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mask = (1 << size) - 1;
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/* all bits must be zero to allow the I/O */
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if ((val & mask) != 0) {
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fail:
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raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr);
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}
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}
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