emulate occ common area region with occ sram device model which occ and skiboot uses it to communicate regarding sensors, slw and HWMON in PowerNV emulated host. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> Message-Id: <20190912093056.4516-3-bala24@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
307 lines
9 KiB
C
307 lines
9 KiB
C
/*
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* QEMU PowerPC PowerNV Emulation of a few OCC related registers
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*
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* Copyright (c) 2015-2017, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "target/ppc/cpu.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/pnv_occ.h"
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#define OCB_OCI_OCCMISC 0x4020
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#define OCB_OCI_OCCMISC_AND 0x4021
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#define OCB_OCI_OCCMISC_OR 0x4022
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/* OCC sensors */
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#define OCC_SENSOR_DATA_BLOCK_OFFSET 0x580000
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#define OCC_SENSOR_DATA_VALID 0x580001
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#define OCC_SENSOR_DATA_VERSION 0x580002
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#define OCC_SENSOR_DATA_READING_VERSION 0x580004
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#define OCC_SENSOR_DATA_NR_SENSORS 0x580008
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#define OCC_SENSOR_DATA_NAMES_OFFSET 0x580010
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#define OCC_SENSOR_DATA_READING_PING_OFFSET 0x580014
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#define OCC_SENSOR_DATA_READING_PONG_OFFSET 0x58000c
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#define OCC_SENSOR_DATA_NAME_LENGTH 0x58000d
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#define OCC_SENSOR_NAME_STRUCTURE_TYPE 0x580023
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#define OCC_SENSOR_LOC_CORE 0x580022
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#define OCC_SENSOR_LOC_GPU 0x580020
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#define OCC_SENSOR_TYPE_POWER 0x580003
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#define OCC_SENSOR_NAME 0x580005
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#define HWMON_SENSORS_MASK 0x58001e
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#define SLW_IMAGE_BASE 0x0
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static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
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{
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bool irq_state;
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PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
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val &= 0xffff000000000000ull;
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occ->occmisc = val;
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irq_state = !!(val >> 63);
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pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
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}
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static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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switch (offset) {
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case OCB_OCI_OCCMISC:
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val = occ->occmisc;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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return val;
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}
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static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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switch (offset) {
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case OCB_OCI_OCCMISC_AND:
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pnv_occ_set_misc(occ, occ->occmisc & val);
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break;
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case OCB_OCI_OCCMISC_OR:
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pnv_occ_set_misc(occ, occ->occmisc | val);
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break;
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case OCB_OCI_OCCMISC:
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pnv_occ_set_misc(occ, val);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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static uint64_t pnv_occ_common_area_read(void *opaque, hwaddr addr,
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unsigned width)
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{
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switch (addr) {
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/*
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* occ-sensor sanity check that asserts the sensor
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* header block
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*/
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case OCC_SENSOR_DATA_BLOCK_OFFSET:
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case OCC_SENSOR_DATA_VALID:
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case OCC_SENSOR_DATA_VERSION:
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case OCC_SENSOR_DATA_READING_VERSION:
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case OCC_SENSOR_DATA_NR_SENSORS:
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case OCC_SENSOR_DATA_NAMES_OFFSET:
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case OCC_SENSOR_DATA_READING_PING_OFFSET:
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case OCC_SENSOR_DATA_READING_PONG_OFFSET:
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case OCC_SENSOR_NAME_STRUCTURE_TYPE:
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return 1;
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case OCC_SENSOR_DATA_NAME_LENGTH:
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return 0x30;
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case OCC_SENSOR_LOC_CORE:
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return 0x0040;
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case OCC_SENSOR_TYPE_POWER:
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return 0x0080;
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case OCC_SENSOR_NAME:
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return 0x1000;
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case HWMON_SENSORS_MASK:
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case OCC_SENSOR_LOC_GPU:
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return 0x8e00;
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case SLW_IMAGE_BASE:
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return 0x1000000000000000;
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}
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return 0;
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}
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static void pnv_occ_common_area_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned width)
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{
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/* callback function defined to occ common area write */
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return;
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}
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static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
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.read = pnv_occ_power8_xscom_read,
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.write = pnv_occ_power8_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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const MemoryRegionOps pnv_occ_sram_ops = {
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.read = pnv_occ_common_area_read,
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.write = pnv_occ_common_area_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
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{
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PnvOCCClass *poc = PNV_OCC_CLASS(klass);
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poc->xscom_size = PNV_XSCOM_OCC_SIZE;
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poc->sram_size = PNV_OCC_COMMON_AREA_SIZE;
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poc->xscom_ops = &pnv_occ_power8_xscom_ops;
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poc->sram_ops = &pnv_occ_sram_ops;
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poc->psi_irq = PSIHB_IRQ_OCC;
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}
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static const TypeInfo pnv_occ_power8_type_info = {
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.name = TYPE_PNV8_OCC,
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.parent = TYPE_PNV_OCC,
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.instance_size = sizeof(PnvOCC),
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.class_init = pnv_occ_power8_class_init,
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};
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#define P9_OCB_OCI_OCCMISC 0x6080
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#define P9_OCB_OCI_OCCMISC_CLEAR 0x6081
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#define P9_OCB_OCI_OCCMISC_OR 0x6082
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static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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switch (offset) {
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case P9_OCB_OCI_OCCMISC:
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val = occ->occmisc;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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return val;
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}
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static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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switch (offset) {
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case P9_OCB_OCI_OCCMISC_CLEAR:
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pnv_occ_set_misc(occ, 0);
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break;
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case P9_OCB_OCI_OCCMISC_OR:
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pnv_occ_set_misc(occ, occ->occmisc | val);
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break;
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case P9_OCB_OCI_OCCMISC:
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pnv_occ_set_misc(occ, val);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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}
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static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
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.read = pnv_occ_power9_xscom_read,
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.write = pnv_occ_power9_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
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{
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PnvOCCClass *poc = PNV_OCC_CLASS(klass);
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poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
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poc->sram_size = PNV9_OCC_COMMON_AREA_SIZE;
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poc->xscom_ops = &pnv_occ_power9_xscom_ops;
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poc->sram_ops = &pnv_occ_sram_ops;
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poc->psi_irq = PSIHB9_IRQ_OCC;
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}
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static const TypeInfo pnv_occ_power9_type_info = {
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.name = TYPE_PNV9_OCC,
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.parent = TYPE_PNV_OCC,
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.instance_size = sizeof(PnvOCC),
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.class_init = pnv_occ_power9_class_init,
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};
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static void pnv_occ_realize(DeviceState *dev, Error **errp)
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{
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PnvOCC *occ = PNV_OCC(dev);
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PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
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Object *obj;
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Error *local_err = NULL;
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occ->occmisc = 0;
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obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
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if (!obj) {
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error_propagate(errp, local_err);
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error_prepend(errp, "required link 'psi' not found: ");
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return;
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}
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occ->psi = PNV_PSI(obj);
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/* XScom region for OCC registers */
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pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
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occ, "xscom-occ", poc->xscom_size);
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/* XScom region for OCC SRAM registers */
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pnv_xscom_region_init(&occ->sram_regs, OBJECT(dev), poc->sram_ops,
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occ, "occ-common-area", poc->sram_size);
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}
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static void pnv_occ_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = pnv_occ_realize;
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dc->desc = "PowerNV OCC Controller";
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}
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static const TypeInfo pnv_occ_type_info = {
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.name = TYPE_PNV_OCC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvOCC),
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.class_init = pnv_occ_class_init,
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.class_size = sizeof(PnvOCCClass),
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.abstract = true,
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};
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static void pnv_occ_register_types(void)
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{
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type_register_static(&pnv_occ_type_info);
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type_register_static(&pnv_occ_power8_type_info);
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type_register_static(&pnv_occ_power9_type_info);
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}
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type_init(pnv_occ_register_types);
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