No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
185 lines
6 KiB
C
185 lines
6 KiB
C
/*
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* Xtensa gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu/log.h"
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enum {
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xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
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xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
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xtRegisterTypeUserReg, /* User defined registers (rur). */
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xtRegisterTypeTieRegfile, /* User define register files. */
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xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
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xtRegisterTypeMapped, /* Mapped on Special Registers. */
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xtRegisterTypeUnmapped, /* Special case of masked registers. */
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xtRegisterTypeWindow, /* Live window registers (a0..a15). */
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xtRegisterTypeVirtual, /* PC, FP. */
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xtRegisterTypeUnknown
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};
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#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
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#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
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#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
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#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
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void xtensa_count_regs(const XtensaConfig *config,
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unsigned *n_regs, unsigned *n_core_regs)
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{
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unsigned i;
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bool count_core_regs = true;
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for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
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if (config->gdb_regmap.reg[i].type != xtRegisterTypeTieState &&
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config->gdb_regmap.reg[i].type != xtRegisterTypeMapped &&
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config->gdb_regmap.reg[i].type != xtRegisterTypeUnmapped) {
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++*n_regs;
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if (count_core_regs) {
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if ((config->gdb_regmap.reg[i].flags &
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XTENSA_REGISTER_FLAGS_PRIVILEGED) == 0) {
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++*n_core_regs;
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} else {
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count_core_regs = false;
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}
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}
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}
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}
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}
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int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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#ifdef CONFIG_USER_ONLY
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int num_regs = env->config->gdb_regmap.num_core_regs;
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#else
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int num_regs = env->config->gdb_regmap.num_regs;
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#endif
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unsigned i;
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if (n < 0 || n >= num_regs) {
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return 0;
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}
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switch (reg->type) {
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case xtRegisterTypeVirtual: /*pc*/
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return gdb_get_reg32(mem_buf, env->pc);
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case xtRegisterTypeArRegfile: /*ar*/
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xtensa_sync_phys_from_window(env);
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return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
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% env->config->nareg]);
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case xtRegisterTypeSpecialReg: /*SR*/
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return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
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case xtRegisterTypeUserReg: /*UR*/
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return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
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case xtRegisterTypeTieRegfile: /*f*/
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i = reg->targno & 0x0f;
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switch (reg->size) {
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case 4:
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return gdb_get_reg32(mem_buf,
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float32_val(env->fregs[i].f32[FP_F32_LOW]));
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case 8:
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return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));
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default:
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qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported size %d\n",
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__func__, n, reg->size);
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memset(mem_buf, 0, reg->size);
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return reg->size;
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}
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case xtRegisterTypeWindow: /*a*/
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return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
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default:
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qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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memset(mem_buf, 0, reg->size);
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return reg->size;
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}
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}
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int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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uint32_t tmp;
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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#ifdef CONFIG_USER_ONLY
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int num_regs = env->config->gdb_regmap.num_core_regs;
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#else
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int num_regs = env->config->gdb_regmap.num_regs;
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#endif
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if (n < 0 || n >= num_regs) {
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return 0;
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}
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tmp = ldl_p(mem_buf);
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switch (reg->type) {
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case xtRegisterTypeVirtual: /*pc*/
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env->pc = tmp;
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break;
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case xtRegisterTypeArRegfile: /*ar*/
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env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
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xtensa_sync_window_from_phys(env);
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break;
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case xtRegisterTypeSpecialReg: /*SR*/
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env->sregs[reg->targno & 0xff] = tmp;
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break;
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case xtRegisterTypeUserReg: /*UR*/
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env->uregs[reg->targno & 0xff] = tmp;
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break;
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case xtRegisterTypeTieRegfile: /*f*/
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switch (reg->size) {
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case 4:
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env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);
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return 4;
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case 8:
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env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);
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return 8;
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default:
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qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported size %d\n",
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__func__, n, reg->size);
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return reg->size;
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}
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case xtRegisterTypeWindow: /*a*/
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env->regs[reg->targno & 0x0f] = tmp;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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return reg->size;
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}
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return 4;
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}
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