This checks if the PCI device retrieved from the PCI device address is VFIO PCI device when enabling EEH functionality. If it's not VFIO PCI device, the EEH functonality isn't enabled. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
281 lines
8.7 KiB
C
281 lines
8.7 KiB
C
/*
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* QEMU sPAPR PCI host for VFIO
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*
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* Copyright (c) 2011-2014 Alexey Kardashevskiy, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License,
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* or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/ppc/spapr.h"
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#include "hw/pci-host/spapr.h"
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#include "hw/pci/msix.h"
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#include "linux/vfio.h"
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#include "hw/vfio/vfio.h"
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static Property spapr_phb_vfio_properties[] = {
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DEFINE_PROP_INT32("iommu", sPAPRPHBVFIOState, iommugroupid, -1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void spapr_phb_vfio_finish_realize(sPAPRPHBState *sphb, Error **errp)
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{
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sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
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struct vfio_iommu_spapr_tce_info info = { .argsz = sizeof(info) };
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int ret;
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sPAPRTCETable *tcet;
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uint32_t liobn = svphb->phb.dma_liobn;
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if (svphb->iommugroupid == -1) {
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error_setg(errp, "Wrong IOMMU group ID %d", svphb->iommugroupid);
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return;
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}
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ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
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VFIO_CHECK_EXTENSION,
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(void *) VFIO_SPAPR_TCE_IOMMU);
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if (ret != 1) {
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error_setg_errno(errp, -ret,
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"spapr-vfio: SPAPR extension is not supported");
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return;
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}
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ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
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VFIO_IOMMU_SPAPR_TCE_GET_INFO, &info);
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if (ret) {
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error_setg_errno(errp, -ret,
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"spapr-vfio: get info from container failed");
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return;
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}
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tcet = spapr_tce_new_table(DEVICE(sphb), liobn, info.dma32_window_start,
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SPAPR_TCE_PAGE_SHIFT,
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info.dma32_window_size >> SPAPR_TCE_PAGE_SHIFT,
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true);
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if (!tcet) {
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error_setg(errp, "spapr-vfio: failed to create VFIO TCE table");
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return;
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}
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/* Register default 32bit DMA window */
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memory_region_add_subregion(&sphb->iommu_root, tcet->bus_offset,
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spapr_tce_get_iommu(tcet));
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}
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static void spapr_phb_vfio_eeh_reenable(sPAPRPHBVFIOState *svphb)
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{
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struct vfio_eeh_pe_op op = {
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.argsz = sizeof(op),
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.op = VFIO_EEH_PE_ENABLE
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};
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vfio_container_ioctl(&svphb->phb.iommu_as,
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svphb->iommugroupid, VFIO_EEH_PE_OP, &op);
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}
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static void spapr_phb_vfio_reset(DeviceState *qdev)
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{
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/*
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* The PE might be in frozen state. To reenable the EEH
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* functionality on it will clean the frozen state, which
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* ensures that the contained PCI devices will work properly
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* after reboot.
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*/
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spapr_phb_vfio_eeh_reenable(SPAPR_PCI_VFIO_HOST_BRIDGE(qdev));
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}
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static int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
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unsigned int addr, int option)
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{
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sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
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struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
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int ret;
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switch (option) {
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case RTAS_EEH_DISABLE:
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op.op = VFIO_EEH_PE_DISABLE;
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break;
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case RTAS_EEH_ENABLE: {
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PCIHostState *phb;
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PCIDevice *pdev;
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/*
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* The EEH functionality is enabled on basis of PCI device,
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* instead of PE. We need check the validity of the PCI
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* device address.
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*/
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phb = PCI_HOST_BRIDGE(sphb);
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pdev = pci_find_device(phb->bus,
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(addr >> 16) & 0xFF, (addr >> 8) & 0xFF);
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if (!pdev || !object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
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return RTAS_OUT_PARAM_ERROR;
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}
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op.op = VFIO_EEH_PE_ENABLE;
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break;
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}
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case RTAS_EEH_THAW_IO:
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op.op = VFIO_EEH_PE_UNFREEZE_IO;
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break;
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case RTAS_EEH_THAW_DMA:
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op.op = VFIO_EEH_PE_UNFREEZE_DMA;
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break;
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default:
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return RTAS_OUT_PARAM_ERROR;
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}
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ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
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VFIO_EEH_PE_OP, &op);
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if (ret < 0) {
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return RTAS_OUT_HW_ERROR;
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}
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return RTAS_OUT_SUCCESS;
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}
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static int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state)
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{
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sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
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struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
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int ret;
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op.op = VFIO_EEH_PE_GET_STATE;
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ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
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VFIO_EEH_PE_OP, &op);
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if (ret < 0) {
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return RTAS_OUT_PARAM_ERROR;
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}
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*state = ret;
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return RTAS_OUT_SUCCESS;
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}
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static void spapr_phb_vfio_eeh_clear_dev_msix(PCIBus *bus,
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PCIDevice *pdev,
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void *opaque)
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{
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/* Check if the device is VFIO PCI device */
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if (!object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
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return;
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}
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/*
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* The MSIx table will be cleaned out by reset. We need
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* disable it so that it can be reenabled properly. Also,
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* the cached MSIx table should be cleared as it's not
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* reflecting the contents in hardware.
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*/
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if (msix_enabled(pdev)) {
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uint16_t flags;
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flags = pci_host_config_read_common(pdev,
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pdev->msix_cap + PCI_MSIX_FLAGS,
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pci_config_size(pdev), 2);
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flags &= ~PCI_MSIX_FLAGS_ENABLE;
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pci_host_config_write_common(pdev,
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pdev->msix_cap + PCI_MSIX_FLAGS,
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pci_config_size(pdev), flags, 2);
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}
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msix_reset(pdev);
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}
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static void spapr_phb_vfio_eeh_clear_bus_msix(PCIBus *bus, void *opaque)
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{
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pci_for_each_device(bus, pci_bus_num(bus),
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spapr_phb_vfio_eeh_clear_dev_msix, NULL);
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}
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static void spapr_phb_vfio_eeh_pre_reset(sPAPRPHBState *sphb)
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{
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PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
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pci_for_each_bus(phb->bus, spapr_phb_vfio_eeh_clear_bus_msix, NULL);
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}
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static int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
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{
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sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
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struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
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int ret;
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switch (option) {
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case RTAS_SLOT_RESET_DEACTIVATE:
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op.op = VFIO_EEH_PE_RESET_DEACTIVATE;
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break;
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case RTAS_SLOT_RESET_HOT:
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spapr_phb_vfio_eeh_pre_reset(sphb);
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op.op = VFIO_EEH_PE_RESET_HOT;
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break;
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case RTAS_SLOT_RESET_FUNDAMENTAL:
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spapr_phb_vfio_eeh_pre_reset(sphb);
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op.op = VFIO_EEH_PE_RESET_FUNDAMENTAL;
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break;
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default:
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return RTAS_OUT_PARAM_ERROR;
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}
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ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
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VFIO_EEH_PE_OP, &op);
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if (ret < 0) {
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return RTAS_OUT_HW_ERROR;
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}
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return RTAS_OUT_SUCCESS;
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}
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static int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
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{
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sPAPRPHBVFIOState *svphb = SPAPR_PCI_VFIO_HOST_BRIDGE(sphb);
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struct vfio_eeh_pe_op op = { .argsz = sizeof(op) };
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int ret;
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op.op = VFIO_EEH_PE_CONFIGURE;
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ret = vfio_container_ioctl(&svphb->phb.iommu_as, svphb->iommugroupid,
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VFIO_EEH_PE_OP, &op);
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if (ret < 0) {
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return RTAS_OUT_PARAM_ERROR;
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}
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return RTAS_OUT_SUCCESS;
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}
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static void spapr_phb_vfio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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sPAPRPHBClass *spc = SPAPR_PCI_HOST_BRIDGE_CLASS(klass);
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dc->props = spapr_phb_vfio_properties;
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dc->reset = spapr_phb_vfio_reset;
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spc->finish_realize = spapr_phb_vfio_finish_realize;
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spc->eeh_set_option = spapr_phb_vfio_eeh_set_option;
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spc->eeh_get_state = spapr_phb_vfio_eeh_get_state;
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spc->eeh_reset = spapr_phb_vfio_eeh_reset;
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spc->eeh_configure = spapr_phb_vfio_eeh_configure;
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}
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static const TypeInfo spapr_phb_vfio_info = {
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.name = TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE,
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.parent = TYPE_SPAPR_PCI_HOST_BRIDGE,
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.instance_size = sizeof(sPAPRPHBVFIOState),
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.class_init = spapr_phb_vfio_class_init,
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.class_size = sizeof(sPAPRPHBClass),
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};
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static void spapr_pci_vfio_register_types(void)
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{
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type_register_static(&spapr_phb_vfio_info);
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}
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type_init(spapr_pci_vfio_register_types)
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