From the very beginning, post_load() was called from common reset. This is not standard and obliged to discriminate the reset case from the restore case using the iidr value. Let's get rid of that call. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1511883692-11511-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
159 lines
4.9 KiB
C
159 lines
4.9 KiB
C
/*
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* ITS base class for a GICv3-based system
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Pavel Fedin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/msi.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "qemu/log.h"
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static int gicv3_its_pre_save(void *opaque)
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{
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GICv3ITSState *s = (GICv3ITSState *)opaque;
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GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
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if (c->pre_save) {
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c->pre_save(s);
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}
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return 0;
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}
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static int gicv3_its_post_load(void *opaque, int version_id)
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{
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GICv3ITSState *s = (GICv3ITSState *)opaque;
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GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
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if (c->post_load) {
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c->post_load(s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_its = {
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.name = "arm_gicv3_its",
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.pre_save = gicv3_its_pre_save,
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.post_load = gicv3_its_post_load,
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.priority = MIG_PRI_GICV3_ITS,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ctlr, GICv3ITSState),
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VMSTATE_UINT32(iidr, GICv3ITSState),
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VMSTATE_UINT64(cbaser, GICv3ITSState),
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VMSTATE_UINT64(cwriter, GICv3ITSState),
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VMSTATE_UINT64(creadr, GICv3ITSState),
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VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
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VMSTATE_END_OF_LIST()
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},
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};
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static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
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return MEMTX_ERROR;
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}
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static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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if (offset == 0x0040 && ((size == 2) || (size == 4))) {
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
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GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
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int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
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if (ret <= 0) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ITS: Error sending MSI: %s\n", strerror(-ret));
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return MEMTX_DECODE_ERROR;
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}
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return MEMTX_OK;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ITS write at bad offset 0x%"PRIx64"\n", offset);
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return MEMTX_DECODE_ERROR;
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}
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}
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static const MemoryRegionOps gicv3_its_trans_ops = {
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.read_with_attrs = gicv3_its_trans_read,
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.write_with_attrs = gicv3_its_trans_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
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"control", ITS_CONTROL_SIZE);
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memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
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&gicv3_its_trans_ops, s,
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"translation", ITS_TRANS_SIZE);
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/* Our two regions are always adjacent, therefore we now combine them
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* into a single one in order to make our users' life easier.
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*/
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memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
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memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
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memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
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&s->iomem_its_translation);
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sysbus_init_mmio(sbd, &s->iomem_main);
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msi_nonbroken = true;
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}
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static void gicv3_its_common_reset(DeviceState *dev)
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{
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GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
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s->ctlr = 0;
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s->cbaser = 0;
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s->cwriter = 0;
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s->creadr = 0;
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s->iidr = 0;
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memset(&s->baser, 0, sizeof(s->baser));
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}
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static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = gicv3_its_common_reset;
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dc->vmsd = &vmstate_its;
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}
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static const TypeInfo gicv3_its_common_info = {
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.name = TYPE_ARM_GICV3_ITS_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GICv3ITSState),
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.class_size = sizeof(GICv3ITSCommonClass),
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.class_init = gicv3_its_common_class_init,
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.abstract = true,
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};
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static void gicv3_its_common_register_types(void)
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{
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type_register_static(&gicv3_its_common_info);
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}
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type_init(gicv3_its_common_register_types)
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