xics_get_qirq() is only used by the sPAPR machine. Let's move it there and change its name to reflect its scope. It will be useful for XIVE support which will use its own set of qirqs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
740 lines
18 KiB
C
740 lines
18 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "trace.h"
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#include "qemu/timer.h"
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#include "hw/ppc/xics.h"
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#include "qemu/error-report.h"
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#include "qapi/visitor.h"
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#include "monitor/monitor.h"
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#include "hw/intc/intc.h"
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void icp_pic_print_info(ICPState *icp, Monitor *mon)
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{
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ICPStateClass *icpc = ICP_GET_CLASS(icp);
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int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
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if (!icp->output) {
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return;
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}
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if (icpc->synchronize_state) {
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icpc->synchronize_state(icp);
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}
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monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
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cpu_index, icp->xirr, icp->xirr_owner,
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icp->pending_priority, icp->mfrr);
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}
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void ics_pic_print_info(ICSState *ics, Monitor *mon)
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{
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ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
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uint32_t i;
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monitor_printf(mon, "ICS %4x..%4x %p\n",
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ics->offset, ics->offset + ics->nr_irqs - 1, ics);
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if (!ics->irqs) {
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return;
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}
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if (icsc->synchronize_state) {
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icsc->synchronize_state(ics);
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}
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for (i = 0; i < ics->nr_irqs; i++) {
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ICSIRQState *irq = ics->irqs + i;
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if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
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continue;
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}
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monitor_printf(mon, " %4x %s %02x %02x\n",
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ics->offset + i,
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(irq->flags & XICS_FLAGS_IRQ_LSI) ?
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"LSI" : "MSI",
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irq->priority, irq->status);
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}
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}
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/*
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* ICP: Presentation layer
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*/
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#define XISR_MASK 0x00ffffff
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#define CPPR_MASK 0xff000000
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#define XISR(icp) (((icp)->xirr) & XISR_MASK)
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#define CPPR(icp) (((icp)->xirr) >> 24)
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static void ics_reject(ICSState *ics, uint32_t nr)
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{
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ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
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if (k->reject) {
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k->reject(ics, nr);
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}
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}
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void ics_resend(ICSState *ics)
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{
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ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
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if (k->resend) {
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k->resend(ics);
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}
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}
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static void ics_eoi(ICSState *ics, int nr)
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{
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ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
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if (k->eoi) {
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k->eoi(ics, nr);
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}
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}
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static void icp_check_ipi(ICPState *icp)
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{
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if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
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return;
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}
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trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
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if (XISR(icp) && icp->xirr_owner) {
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ics_reject(icp->xirr_owner, XISR(icp));
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}
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icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
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icp->pending_priority = icp->mfrr;
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icp->xirr_owner = NULL;
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qemu_irq_raise(icp->output);
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}
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void icp_resend(ICPState *icp)
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{
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XICSFabric *xi = icp->xics;
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XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
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if (icp->mfrr < CPPR(icp)) {
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icp_check_ipi(icp);
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}
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xic->ics_resend(xi);
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}
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void icp_set_cppr(ICPState *icp, uint8_t cppr)
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{
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uint8_t old_cppr;
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uint32_t old_xisr;
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old_cppr = CPPR(icp);
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icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
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if (cppr < old_cppr) {
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if (XISR(icp) && (cppr <= icp->pending_priority)) {
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old_xisr = XISR(icp);
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icp->xirr &= ~XISR_MASK; /* Clear XISR */
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icp->pending_priority = 0xff;
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qemu_irq_lower(icp->output);
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if (icp->xirr_owner) {
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ics_reject(icp->xirr_owner, old_xisr);
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icp->xirr_owner = NULL;
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}
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}
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} else {
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if (!XISR(icp)) {
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icp_resend(icp);
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}
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}
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}
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void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
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{
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icp->mfrr = mfrr;
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if (mfrr < CPPR(icp)) {
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icp_check_ipi(icp);
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}
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}
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uint32_t icp_accept(ICPState *icp)
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{
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uint32_t xirr = icp->xirr;
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qemu_irq_lower(icp->output);
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icp->xirr = icp->pending_priority << 24;
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icp->pending_priority = 0xff;
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icp->xirr_owner = NULL;
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trace_xics_icp_accept(xirr, icp->xirr);
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return xirr;
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}
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uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
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{
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if (mfrr) {
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*mfrr = icp->mfrr;
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}
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return icp->xirr;
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}
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void icp_eoi(ICPState *icp, uint32_t xirr)
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{
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XICSFabric *xi = icp->xics;
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XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
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ICSState *ics;
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uint32_t irq;
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/* Send EOI -> ICS */
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icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
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trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
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irq = xirr & XISR_MASK;
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ics = xic->ics_get(xi, irq);
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if (ics) {
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ics_eoi(ics, irq);
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}
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if (!XISR(icp)) {
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icp_resend(icp);
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}
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}
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static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
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{
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ICPState *icp = xics_icp_get(ics->xics, server);
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trace_xics_icp_irq(server, nr, priority);
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if ((priority >= CPPR(icp))
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|| (XISR(icp) && (icp->pending_priority <= priority))) {
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ics_reject(ics, nr);
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} else {
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if (XISR(icp) && icp->xirr_owner) {
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ics_reject(icp->xirr_owner, XISR(icp));
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icp->xirr_owner = NULL;
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}
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icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
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icp->xirr_owner = ics;
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icp->pending_priority = priority;
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trace_xics_icp_raise(icp->xirr, icp->pending_priority);
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qemu_irq_raise(icp->output);
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}
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}
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static int icp_dispatch_pre_save(void *opaque)
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{
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ICPState *icp = opaque;
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ICPStateClass *info = ICP_GET_CLASS(icp);
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if (info->pre_save) {
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info->pre_save(icp);
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}
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return 0;
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}
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static int icp_dispatch_post_load(void *opaque, int version_id)
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{
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ICPState *icp = opaque;
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ICPStateClass *info = ICP_GET_CLASS(icp);
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if (info->post_load) {
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return info->post_load(icp, version_id);
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}
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return 0;
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}
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static const VMStateDescription vmstate_icp_server = {
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.name = "icp/server",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = icp_dispatch_pre_save,
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.post_load = icp_dispatch_post_load,
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.fields = (VMStateField[]) {
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/* Sanity check */
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VMSTATE_UINT32(xirr, ICPState),
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VMSTATE_UINT8(pending_priority, ICPState),
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VMSTATE_UINT8(mfrr, ICPState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void icp_reset(void *dev)
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{
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ICPState *icp = ICP(dev);
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ICPStateClass *icpc = ICP_GET_CLASS(icp);
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icp->xirr = 0;
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icp->pending_priority = 0xff;
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icp->mfrr = 0xff;
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/* Make all outputs are deasserted */
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qemu_set_irq(icp->output, 0);
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if (icpc->reset) {
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icpc->reset(icp);
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}
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}
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static void icp_realize(DeviceState *dev, Error **errp)
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{
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ICPState *icp = ICP(dev);
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ICPStateClass *icpc = ICP_GET_CLASS(dev);
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PowerPCCPU *cpu;
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CPUPPCState *env;
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Object *obj;
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Error *err = NULL;
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obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
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if (!obj) {
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error_propagate(errp, err);
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error_prepend(errp, "required link '" ICP_PROP_XICS "' not found: ");
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return;
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}
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icp->xics = XICS_FABRIC(obj);
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obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
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if (!obj) {
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error_propagate(errp, err);
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error_prepend(errp, "required link '" ICP_PROP_CPU "' not found: ");
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return;
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}
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cpu = POWERPC_CPU(obj);
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icp->cs = CPU(obj);
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env = &cpu->env;
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_POWER7:
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icp->output = env->irq_inputs[POWER7_INPUT_INT];
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break;
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case PPC_FLAGS_INPUT_970:
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icp->output = env->irq_inputs[PPC970_INPUT_INT];
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break;
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default:
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error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
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return;
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}
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if (icpc->realize) {
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icpc->realize(icp, errp);
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}
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qemu_register_reset(icp_reset, dev);
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vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
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}
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static void icp_unrealize(DeviceState *dev, Error **errp)
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{
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ICPState *icp = ICP(dev);
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vmstate_unregister(NULL, &vmstate_icp_server, icp);
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qemu_unregister_reset(icp_reset, dev);
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}
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static void icp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = icp_realize;
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dc->unrealize = icp_unrealize;
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}
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static const TypeInfo icp_info = {
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.name = TYPE_ICP,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(ICPState),
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.class_init = icp_class_init,
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.class_size = sizeof(ICPStateClass),
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};
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Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
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{
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Error *local_err = NULL;
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Object *obj;
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obj = object_new(type);
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object_property_add_child(cpu, type, obj, &error_abort);
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object_unref(obj);
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object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
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&error_abort);
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object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
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object_property_set_bool(obj, true, "realized", &local_err);
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if (local_err) {
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object_unparent(obj);
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error_propagate(errp, local_err);
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obj = NULL;
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}
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return obj;
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}
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/*
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* ICS: Source layer
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*/
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static void ics_simple_resend_msi(ICSState *ics, int srcno)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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/* FIXME: filter by server#? */
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if (irq->status & XICS_STATUS_REJECTED) {
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irq->status &= ~XICS_STATUS_REJECTED;
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if (irq->priority != 0xff) {
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icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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}
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static void ics_simple_resend_lsi(ICSState *ics, int srcno)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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if ((irq->priority != 0xff)
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&& (irq->status & XICS_STATUS_ASSERTED)
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&& !(irq->status & XICS_STATUS_SENT)) {
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irq->status |= XICS_STATUS_SENT;
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icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
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if (val) {
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if (irq->priority == 0xff) {
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irq->status |= XICS_STATUS_MASKED_PENDING;
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trace_xics_masked_pending();
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} else {
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icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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}
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static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
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if (val) {
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irq->status |= XICS_STATUS_ASSERTED;
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} else {
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irq->status &= ~XICS_STATUS_ASSERTED;
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}
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ics_simple_resend_lsi(ics, srcno);
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}
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static void ics_simple_set_irq(void *opaque, int srcno, int val)
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{
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ICSState *ics = (ICSState *)opaque;
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if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
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ics_simple_set_irq_lsi(ics, srcno, val);
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} else {
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ics_simple_set_irq_msi(ics, srcno, val);
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}
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}
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static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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if (!(irq->status & XICS_STATUS_MASKED_PENDING)
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|| (irq->priority == 0xff)) {
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return;
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}
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irq->status &= ~XICS_STATUS_MASKED_PENDING;
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icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
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}
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static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
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{
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ics_simple_resend_lsi(ics, srcno);
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}
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void ics_simple_write_xive(ICSState *ics, int srcno, int server,
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uint8_t priority, uint8_t saved_priority)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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irq->server = server;
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irq->priority = priority;
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irq->saved_priority = saved_priority;
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|
trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
|
|
priority);
|
|
|
|
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
|
|
ics_simple_write_xive_lsi(ics, srcno);
|
|
} else {
|
|
ics_simple_write_xive_msi(ics, srcno);
|
|
}
|
|
}
|
|
|
|
static void ics_simple_reject(ICSState *ics, uint32_t nr)
|
|
{
|
|
ICSIRQState *irq = ics->irqs + nr - ics->offset;
|
|
|
|
trace_xics_ics_simple_reject(nr, nr - ics->offset);
|
|
if (irq->flags & XICS_FLAGS_IRQ_MSI) {
|
|
irq->status |= XICS_STATUS_REJECTED;
|
|
} else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
|
|
irq->status &= ~XICS_STATUS_SENT;
|
|
}
|
|
}
|
|
|
|
static void ics_simple_resend(ICSState *ics)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ics->nr_irqs; i++) {
|
|
/* FIXME: filter by server#? */
|
|
if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
|
|
ics_simple_resend_lsi(ics, i);
|
|
} else {
|
|
ics_simple_resend_msi(ics, i);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void ics_simple_eoi(ICSState *ics, uint32_t nr)
|
|
{
|
|
int srcno = nr - ics->offset;
|
|
ICSIRQState *irq = ics->irqs + srcno;
|
|
|
|
trace_xics_ics_simple_eoi(nr);
|
|
|
|
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
|
|
irq->status &= ~XICS_STATUS_SENT;
|
|
}
|
|
}
|
|
|
|
static void ics_simple_reset(void *dev)
|
|
{
|
|
ICSState *ics = ICS_SIMPLE(dev);
|
|
int i;
|
|
uint8_t flags[ics->nr_irqs];
|
|
|
|
for (i = 0; i < ics->nr_irqs; i++) {
|
|
flags[i] = ics->irqs[i].flags;
|
|
}
|
|
|
|
memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
|
|
|
|
for (i = 0; i < ics->nr_irqs; i++) {
|
|
ics->irqs[i].priority = 0xff;
|
|
ics->irqs[i].saved_priority = 0xff;
|
|
ics->irqs[i].flags = flags[i];
|
|
}
|
|
}
|
|
|
|
static int ics_simple_dispatch_pre_save(void *opaque)
|
|
{
|
|
ICSState *ics = opaque;
|
|
ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
|
|
|
|
if (info->pre_save) {
|
|
info->pre_save(ics);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ics_simple_dispatch_post_load(void *opaque, int version_id)
|
|
{
|
|
ICSState *ics = opaque;
|
|
ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
|
|
|
|
if (info->post_load) {
|
|
return info->post_load(ics, version_id);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_ics_simple_irq = {
|
|
.name = "ics/irq",
|
|
.version_id = 2,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(server, ICSIRQState),
|
|
VMSTATE_UINT8(priority, ICSIRQState),
|
|
VMSTATE_UINT8(saved_priority, ICSIRQState),
|
|
VMSTATE_UINT8(status, ICSIRQState),
|
|
VMSTATE_UINT8(flags, ICSIRQState),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static const VMStateDescription vmstate_ics_simple = {
|
|
.name = "ics",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.pre_save = ics_simple_dispatch_pre_save,
|
|
.post_load = ics_simple_dispatch_post_load,
|
|
.fields = (VMStateField[]) {
|
|
/* Sanity check */
|
|
VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
|
|
|
|
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
|
|
vmstate_ics_simple_irq,
|
|
ICSIRQState),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static void ics_simple_initfn(Object *obj)
|
|
{
|
|
ICSState *ics = ICS_SIMPLE(obj);
|
|
|
|
ics->offset = XICS_IRQ_BASE;
|
|
}
|
|
|
|
static void ics_simple_realize(ICSState *ics, Error **errp)
|
|
{
|
|
if (!ics->nr_irqs) {
|
|
error_setg(errp, "Number of interrupts needs to be greater 0");
|
|
return;
|
|
}
|
|
ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
|
|
ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
|
|
|
|
qemu_register_reset(ics_simple_reset, ics);
|
|
}
|
|
|
|
static Property ics_simple_properties[] = {
|
|
DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ics_simple_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ICSStateClass *isc = ICS_BASE_CLASS(klass);
|
|
|
|
isc->realize = ics_simple_realize;
|
|
dc->props = ics_simple_properties;
|
|
dc->vmsd = &vmstate_ics_simple;
|
|
isc->reject = ics_simple_reject;
|
|
isc->resend = ics_simple_resend;
|
|
isc->eoi = ics_simple_eoi;
|
|
}
|
|
|
|
static const TypeInfo ics_simple_info = {
|
|
.name = TYPE_ICS_SIMPLE,
|
|
.parent = TYPE_ICS_BASE,
|
|
.instance_size = sizeof(ICSState),
|
|
.class_init = ics_simple_class_init,
|
|
.class_size = sizeof(ICSStateClass),
|
|
.instance_init = ics_simple_initfn,
|
|
};
|
|
|
|
static void ics_base_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
|
|
ICSState *ics = ICS_BASE(dev);
|
|
Object *obj;
|
|
Error *err = NULL;
|
|
|
|
obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
|
|
if (!obj) {
|
|
error_propagate(errp, err);
|
|
error_prepend(errp, "required link '" ICS_PROP_XICS "' not found: ");
|
|
return;
|
|
}
|
|
ics->xics = XICS_FABRIC(obj);
|
|
|
|
|
|
if (icsc->realize) {
|
|
icsc->realize(ics, errp);
|
|
}
|
|
}
|
|
|
|
static void ics_base_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = ics_base_realize;
|
|
}
|
|
|
|
static const TypeInfo ics_base_info = {
|
|
.name = TYPE_ICS_BASE,
|
|
.parent = TYPE_DEVICE,
|
|
.abstract = true,
|
|
.instance_size = sizeof(ICSState),
|
|
.class_init = ics_base_class_init,
|
|
.class_size = sizeof(ICSStateClass),
|
|
};
|
|
|
|
static const TypeInfo xics_fabric_info = {
|
|
.name = TYPE_XICS_FABRIC,
|
|
.parent = TYPE_INTERFACE,
|
|
.class_size = sizeof(XICSFabricClass),
|
|
};
|
|
|
|
/*
|
|
* Exported functions
|
|
*/
|
|
ICPState *xics_icp_get(XICSFabric *xi, int server)
|
|
{
|
|
XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
|
|
|
|
return xic->icp_get(xi, server);
|
|
}
|
|
|
|
void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
|
|
{
|
|
assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
|
|
|
|
ics->irqs[srcno].flags |=
|
|
lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
|
|
}
|
|
|
|
static void xics_register_types(void)
|
|
{
|
|
type_register_static(&ics_simple_info);
|
|
type_register_static(&ics_base_info);
|
|
type_register_static(&icp_info);
|
|
type_register_static(&xics_fabric_info);
|
|
}
|
|
|
|
type_init(xics_register_types)
|