We exposed gpex_set_irq_num() for machines to set the INTx to GSI routing. However if the machine forgets to call that function we currently do not check the association was properly done. Let's initialize gsi values to -1 and if this value is found in gpex_route_intx_pin_to_irq, set the routing mode as disabled. Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1508776211-22175-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
188 lines
5.7 KiB
C
188 lines
5.7 KiB
C
/*
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* QEMU Generic PCI Express Bridge Emulation
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*
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* Copyright (C) 2015 Alexander Graf <agraf@suse.de>
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*
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* Code loosely based on q35.c.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Check out these documents for more information on the device:
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*
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* http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt
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* http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/pci-host/gpex.h"
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/****************************************************************************
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* GPEX host
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*/
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static void gpex_set_irq(void *opaque, int irq_num, int level)
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{
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GPEXHost *s = opaque;
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qemu_set_irq(s->irq[irq_num], level);
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}
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int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
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{
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if (index >= GPEX_NUM_IRQS) {
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return -EINVAL;
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}
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s->irq_num[index] = gsi;
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return 0;
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}
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static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
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{
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PCIINTxRoute route;
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GPEXHost *s = opaque;
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int gsi = s->irq_num[pin];
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route.irq = gsi;
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if (gsi < 0) {
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route.mode = PCI_INTX_DISABLED;
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} else {
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route.mode = PCI_INTX_ENABLED;
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}
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return route;
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}
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static void gpex_host_realize(DeviceState *dev, Error **errp)
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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GPEXHost *s = GPEX_HOST(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
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int i;
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pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
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memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
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memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
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sysbus_init_mmio(sbd, &pex->mmio);
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sysbus_init_mmio(sbd, &s->io_mmio);
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sysbus_init_mmio(sbd, &s->io_ioport);
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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sysbus_init_irq(sbd, &s->irq[i]);
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s->irq_num[i] = -1;
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}
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pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,
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pci_swizzle_map_irq_fn, s, &s->io_mmio,
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&s->io_ioport, 0, 4, TYPE_PCIE_BUS);
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qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
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pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
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qdev_init_nofail(DEVICE(&s->gpex_root));
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}
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static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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return "0000:00";
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}
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static void gpex_host_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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hc->root_bus_path = gpex_host_root_bus_path;
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dc->realize = gpex_host_realize;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->fw_name = "pci";
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}
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static void gpex_host_initfn(Object *obj)
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{
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GPEXHost *s = GPEX_HOST(obj);
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GPEXRootState *root = &s->gpex_root;
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object_initialize(root, sizeof(*root), TYPE_GPEX_ROOT_DEVICE);
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object_property_add_child(obj, "gpex_root", OBJECT(root), NULL);
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qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
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qdev_prop_set_bit(DEVICE(root), "multifunction", false);
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}
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static const TypeInfo gpex_host_info = {
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.name = TYPE_GPEX_HOST,
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.parent = TYPE_PCIE_HOST_BRIDGE,
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.instance_size = sizeof(GPEXHost),
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.instance_init = gpex_host_initfn,
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.class_init = gpex_host_class_init,
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};
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/****************************************************************************
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* GPEX Root D0:F0
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*/
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static const VMStateDescription vmstate_gpex_root = {
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.name = "gpex_root",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void gpex_root_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->desc = "QEMU generic PCIe host bridge";
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dc->vmsd = &vmstate_gpex_root;
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k->vendor_id = PCI_VENDOR_ID_REDHAT;
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k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST;
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k->revision = 0;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo gpex_root_info = {
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.name = TYPE_GPEX_ROOT_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(GPEXRootState),
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.class_init = gpex_root_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void gpex_register(void)
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{
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type_register_static(&gpex_root_info);
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type_register_static(&gpex_host_info);
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}
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type_init(gpex_register)
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