fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
89 lines
2.2 KiB
Plaintext
89 lines
2.2 KiB
Plaintext
TODO-list:
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CPU common:
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- Unimplemented features/bugs:
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- Delay slot handling may fail sometimes (branch end of page, delay
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slot next page)
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- Atomical instructions
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- CPU features should match real CPUs (also ASI selection)
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- Optimizations/improvements:
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- Condition code/branch handling like x86, also for FPU?
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- Remove remaining explicit alignment checks
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- Global register for regwptr, so that windowed registers can be
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accessed directly
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- Improve Sparc32plus addressing
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- NPC/PC static optimisations (use JUMP_TB when possible)? (Is this
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obsolete?)
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- Synthetic instructions
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- MMU model dependent on CPU model
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- Select ASI helper at translation time (on V9 only if known)
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- KQemu/KVM support for VM only
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- Hardware breakpoint/watchpoint support
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- Cache emulation mode
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- Reverse-endian pages
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- Faster FPU emulation
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- Busy loop detection
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Sparc32 CPUs:
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- Unimplemented features/bugs:
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- Sun4/Sun4c MMUs
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- Some V8 ASIs
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Sparc64 CPUs:
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- Unimplemented features/bugs:
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- Interrupt handling
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- Secondary address space, other MMU functions
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- Many V9/UA2005/UA2007 ASIs
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- Rest of V9 instructions, missing VIS instructions
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- IG/MG/AG vs. UA2007 globals
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- Full hypervisor support
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- SMP/CMT
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- Sun4v CPUs
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Sun4:
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- To be added
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Sun4c:
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- A lot of unimplemented features
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- Maybe split from Sun4m
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Sun4m:
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- Unimplemented features/bugs:
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- Hardware devices do not match real boards
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- Floppy does not work
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- CS4231: merge with cs4231a, add DMA
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- Add cg6, bwtwo
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- Arbitrary resolution support
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- PCI for MicroSparc-IIe
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- JavaStation machines
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- SBus slot probing, FCode ROM support
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- SMP probing support
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- Interrupt routing does not match real HW
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- SuSE 7.3 keyboard sometimes unresponsive
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- Gentoo 2004.1 SMP does not work
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- SS600MP ledma -> lebuffer
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- Type 5 keyboard
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- Less fixed hardware choices
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- DBRI audio (Am7930)
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- BPP parallel
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- Diagnostic switch
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- ESP PIO mode
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Sun4d:
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- A lot of unimplemented features:
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- SBI
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- IO-unit
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- Maybe split from Sun4m
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Sun4u:
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- Unimplemented features/bugs:
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- Interrupt controller
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- PCI/IOMMU support (Simba, JIO, Tomatillo, Psycho, Schizo, Safari...)
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- SMP
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- Happy Meal Ethernet, flash, I2C, GPIO
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- A lot of real machine types
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Sun4v:
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- A lot of unimplemented features
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- A lot of real machine types
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