Allwinner System-on-Chips usually contain a Real Time Clock (RTC) for non-volatile system date and time keeping. This commit adds a generic Allwinner RTC device that supports the RTC devices found in Allwinner SoC family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc). The following RTC functionality and features are implemented: * Year-Month-Day read/write * Hour-Minute-Second read/write * General Purpose storage The following boards are extended with the RTC device: * Cubieboard (hw/arm/cubieboard.c) * Orange Pi PC (hw/arm/orangepi.c) Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
466 lines
18 KiB
C
466 lines
18 KiB
C
/*
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* Allwinner H3 System on Chip emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "exec/address-spaces.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "hw/qdev-core.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/misc/unimp.h"
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#include "hw/usb/hcd-ehci.h"
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#include "hw/loader.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/allwinner-h3.h"
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/* Memory map */
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const hwaddr allwinner_h3_memmap[] = {
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[AW_H3_SRAM_A1] = 0x00000000,
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[AW_H3_SRAM_A2] = 0x00044000,
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[AW_H3_SRAM_C] = 0x00010000,
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[AW_H3_SYSCTRL] = 0x01c00000,
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[AW_H3_MMC0] = 0x01c0f000,
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[AW_H3_SID] = 0x01c14000,
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[AW_H3_EHCI0] = 0x01c1a000,
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[AW_H3_OHCI0] = 0x01c1a400,
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[AW_H3_EHCI1] = 0x01c1b000,
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[AW_H3_OHCI1] = 0x01c1b400,
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[AW_H3_EHCI2] = 0x01c1c000,
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[AW_H3_OHCI2] = 0x01c1c400,
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[AW_H3_EHCI3] = 0x01c1d000,
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[AW_H3_OHCI3] = 0x01c1d400,
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[AW_H3_CCU] = 0x01c20000,
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[AW_H3_PIT] = 0x01c20c00,
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[AW_H3_UART0] = 0x01c28000,
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[AW_H3_UART1] = 0x01c28400,
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[AW_H3_UART2] = 0x01c28800,
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[AW_H3_UART3] = 0x01c28c00,
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[AW_H3_EMAC] = 0x01c30000,
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[AW_H3_DRAMCOM] = 0x01c62000,
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[AW_H3_DRAMCTL] = 0x01c63000,
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[AW_H3_DRAMPHY] = 0x01c65000,
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[AW_H3_GIC_DIST] = 0x01c81000,
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[AW_H3_GIC_CPU] = 0x01c82000,
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[AW_H3_GIC_HYP] = 0x01c84000,
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[AW_H3_GIC_VCPU] = 0x01c86000,
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[AW_H3_RTC] = 0x01f00000,
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[AW_H3_CPUCFG] = 0x01f01c00,
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[AW_H3_SDRAM] = 0x40000000
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};
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/* List of unimplemented devices */
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struct AwH3Unimplemented {
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const char *device_name;
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hwaddr base;
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hwaddr size;
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} unimplemented[] = {
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{ "d-engine", 0x01000000, 4 * MiB },
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{ "d-inter", 0x01400000, 128 * KiB },
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{ "dma", 0x01c02000, 4 * KiB },
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{ "nfdc", 0x01c03000, 4 * KiB },
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{ "ts", 0x01c06000, 4 * KiB },
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{ "keymem", 0x01c0b000, 4 * KiB },
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{ "lcd0", 0x01c0c000, 4 * KiB },
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{ "lcd1", 0x01c0d000, 4 * KiB },
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{ "ve", 0x01c0e000, 4 * KiB },
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{ "mmc1", 0x01c10000, 4 * KiB },
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{ "mmc2", 0x01c11000, 4 * KiB },
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{ "crypto", 0x01c15000, 4 * KiB },
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{ "msgbox", 0x01c17000, 4 * KiB },
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{ "spinlock", 0x01c18000, 4 * KiB },
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{ "usb0-otg", 0x01c19000, 4 * KiB },
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{ "usb0-phy", 0x01c1a000, 4 * KiB },
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{ "usb1-phy", 0x01c1b000, 4 * KiB },
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{ "usb2-phy", 0x01c1c000, 4 * KiB },
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{ "usb3-phy", 0x01c1d000, 4 * KiB },
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{ "smc", 0x01c1e000, 4 * KiB },
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{ "pio", 0x01c20800, 1 * KiB },
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{ "owa", 0x01c21000, 1 * KiB },
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{ "pwm", 0x01c21400, 1 * KiB },
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{ "keyadc", 0x01c21800, 1 * KiB },
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{ "pcm0", 0x01c22000, 1 * KiB },
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{ "pcm1", 0x01c22400, 1 * KiB },
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{ "pcm2", 0x01c22800, 1 * KiB },
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{ "audio", 0x01c22c00, 2 * KiB },
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{ "smta", 0x01c23400, 1 * KiB },
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{ "ths", 0x01c25000, 1 * KiB },
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{ "uart0", 0x01c28000, 1 * KiB },
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{ "uart1", 0x01c28400, 1 * KiB },
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{ "uart2", 0x01c28800, 1 * KiB },
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{ "uart3", 0x01c28c00, 1 * KiB },
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{ "twi0", 0x01c2ac00, 1 * KiB },
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{ "twi1", 0x01c2b000, 1 * KiB },
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{ "twi2", 0x01c2b400, 1 * KiB },
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{ "scr", 0x01c2c400, 1 * KiB },
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{ "gpu", 0x01c40000, 64 * KiB },
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{ "hstmr", 0x01c60000, 4 * KiB },
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{ "spi0", 0x01c68000, 4 * KiB },
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{ "spi1", 0x01c69000, 4 * KiB },
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{ "csi", 0x01cb0000, 320 * KiB },
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{ "tve", 0x01e00000, 64 * KiB },
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{ "hdmi", 0x01ee0000, 128 * KiB },
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{ "r_timer", 0x01f00800, 1 * KiB },
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{ "r_intc", 0x01f00c00, 1 * KiB },
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{ "r_wdog", 0x01f01000, 1 * KiB },
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{ "r_prcm", 0x01f01400, 1 * KiB },
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{ "r_twd", 0x01f01800, 1 * KiB },
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{ "r_cir-rx", 0x01f02000, 1 * KiB },
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{ "r_twi", 0x01f02400, 1 * KiB },
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{ "r_uart", 0x01f02800, 1 * KiB },
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{ "r_pio", 0x01f02c00, 1 * KiB },
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{ "r_pwm", 0x01f03800, 1 * KiB },
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{ "core-dbg", 0x3f500000, 128 * KiB },
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{ "tsgen-ro", 0x3f506000, 4 * KiB },
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{ "tsgen-ctl", 0x3f507000, 4 * KiB },
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{ "ddr-mem", 0x40000000, 2 * GiB },
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{ "n-brom", 0xffff0000, 32 * KiB },
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{ "s-brom", 0xffff0000, 64 * KiB }
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};
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/* Per Processor Interrupts */
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enum {
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AW_H3_GIC_PPI_MAINT = 9,
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AW_H3_GIC_PPI_HYPTIMER = 10,
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AW_H3_GIC_PPI_VIRTTIMER = 11,
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AW_H3_GIC_PPI_SECTIMER = 13,
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AW_H3_GIC_PPI_PHYSTIMER = 14
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};
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/* Shared Processor Interrupts */
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enum {
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AW_H3_GIC_SPI_UART0 = 0,
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AW_H3_GIC_SPI_UART1 = 1,
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AW_H3_GIC_SPI_UART2 = 2,
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AW_H3_GIC_SPI_UART3 = 3,
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AW_H3_GIC_SPI_TIMER0 = 18,
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AW_H3_GIC_SPI_TIMER1 = 19,
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AW_H3_GIC_SPI_MMC0 = 60,
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AW_H3_GIC_SPI_EHCI0 = 72,
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AW_H3_GIC_SPI_OHCI0 = 73,
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AW_H3_GIC_SPI_EHCI1 = 74,
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AW_H3_GIC_SPI_OHCI1 = 75,
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AW_H3_GIC_SPI_EHCI2 = 76,
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AW_H3_GIC_SPI_OHCI2 = 77,
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AW_H3_GIC_SPI_EHCI3 = 78,
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AW_H3_GIC_SPI_OHCI3 = 79,
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AW_H3_GIC_SPI_EMAC = 82
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};
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/* Allwinner H3 general constants */
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enum {
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AW_H3_GIC_NUM_SPI = 128
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};
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void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
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{
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const int64_t rom_size = 32 * KiB;
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g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
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if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
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error_setg(&error_fatal, "%s: failed to read BlockBackend data",
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__func__);
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return;
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}
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rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
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rom_size, s->memmap[AW_H3_SRAM_A1],
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NULL, NULL, NULL, NULL, false);
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}
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static void allwinner_h3_init(Object *obj)
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{
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AwH3State *s = AW_H3(obj);
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s->memmap = allwinner_h3_memmap;
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for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
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object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
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ARM_CPU_TYPE_NAME("cortex-a7"),
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&error_abort, NULL);
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}
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sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
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TYPE_ARM_GIC);
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sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
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TYPE_AW_A10_PIT);
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object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
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"clk0-freq", &error_abort);
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object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
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"clk1-freq", &error_abort);
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sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
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TYPE_AW_H3_CCU);
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sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
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TYPE_AW_H3_SYSCTRL);
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sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
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TYPE_AW_CPUCFG);
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sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
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TYPE_AW_SID);
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object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
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"identifier", &error_abort);
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sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
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TYPE_AW_SDHOST_SUN5I);
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sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
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TYPE_AW_SUN8I_EMAC);
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sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
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TYPE_AW_H3_DRAMC);
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object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
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"ram-addr", &error_abort);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
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"ram-size", &error_abort);
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sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
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TYPE_AW_RTC_SUN6I);
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}
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static void allwinner_h3_realize(DeviceState *dev, Error **errp)
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{
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AwH3State *s = AW_H3(dev);
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unsigned i;
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/* CPUs */
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for (i = 0; i < AW_H3_NUM_CPUS; i++) {
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/* Provide Power State Coordination Interface */
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qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
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QEMU_PSCI_CONDUIT_HVC);
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/* Disable secondary CPUs */
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qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
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i > 0);
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/* All exception levels required */
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qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
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qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
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/* Mark realized */
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qdev_init_nofail(DEVICE(&s->cpus[i]));
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}
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/* Generic Interrupt Controller */
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
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GIC_INTERNAL);
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
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qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
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qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
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qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
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qdev_init_nofail(DEVICE(&s->gic));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
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/*
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* Wire the outputs from each CPU's generic timer and the GICv3
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* maintenance interrupt signal to the appropriate GIC PPI inputs,
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* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
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*/
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for (i = 0; i < AW_H3_NUM_CPUS; i++) {
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DeviceState *cpudev = DEVICE(&s->cpus[i]);
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int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
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int irq;
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/*
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* Mapping from the output timer irq lines from the CPU to the
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* GIC PPI inputs used for this board.
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*/
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const int timer_irq[] = {
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[GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
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[GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
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[GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
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[GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
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};
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/* Connect CPU timer outputs to GIC PPI inputs */
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for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
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qdev_connect_gpio_out(cpudev, irq,
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qdev_get_gpio_in(DEVICE(&s->gic),
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ppibase + timer_irq[irq]));
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}
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/* Connect GIC outputs to CPU interrupt inputs */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
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qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
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qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
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qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
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qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
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/* GIC maintenance signal */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
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qdev_get_gpio_in(DEVICE(&s->gic),
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ppibase + AW_H3_GIC_PPI_MAINT));
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}
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/* Timer */
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qdev_init_nofail(DEVICE(&s->timer));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
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qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
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qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
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/* SRAM */
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memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
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64 * KiB, &error_abort);
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memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
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32 * KiB, &error_abort);
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memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
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44 * KiB, &error_abort);
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memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
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&s->sram_a1);
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memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
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&s->sram_a2);
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memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
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&s->sram_c);
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/* Clock Control Unit */
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qdev_init_nofail(DEVICE(&s->ccu));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
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/* System Control */
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qdev_init_nofail(DEVICE(&s->sysctrl));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
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/* CPU Configuration */
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qdev_init_nofail(DEVICE(&s->cpucfg));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
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/* Security Identifier */
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qdev_init_nofail(DEVICE(&s->sid));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
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/* SD/MMC */
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qdev_init_nofail(DEVICE(&s->mmc0));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
|
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
|
|
|
|
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
|
|
"sd-bus", &error_abort);
|
|
|
|
/* EMAC */
|
|
if (nd_table[0].used) {
|
|
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
|
|
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
|
|
}
|
|
qdev_init_nofail(DEVICE(&s->emac));
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
|
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
|
|
|
|
/* Universal Serial Bus */
|
|
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_EHCI0));
|
|
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_EHCI1));
|
|
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_EHCI2));
|
|
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_EHCI3));
|
|
|
|
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_OHCI0));
|
|
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_OHCI1));
|
|
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_OHCI2));
|
|
sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
|
|
qdev_get_gpio_in(DEVICE(&s->gic),
|
|
AW_H3_GIC_SPI_OHCI3));
|
|
|
|
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
|
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
|
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
|
|
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
|
/* UART1 */
|
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
|
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
|
|
115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
|
|
/* UART2 */
|
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
|
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
|
|
115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
|
|
/* UART3 */
|
|
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
|
|
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
|
|
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
|
|
|
|
/* DRAMC */
|
|
qdev_init_nofail(DEVICE(&s->dramc));
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
|
|
|
|
/* RTC */
|
|
qdev_init_nofail(DEVICE(&s->rtc));
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
|
|
|
|
/* Unimplemented devices */
|
|
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
|
|
create_unimplemented_device(unimplemented[i].device_name,
|
|
unimplemented[i].base,
|
|
unimplemented[i].size);
|
|
}
|
|
}
|
|
|
|
static void allwinner_h3_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = allwinner_h3_realize;
|
|
/* Reason: uses serial_hd() in realize function */
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo allwinner_h3_type_info = {
|
|
.name = TYPE_AW_H3,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(AwH3State),
|
|
.instance_init = allwinner_h3_init,
|
|
.class_init = allwinner_h3_class_init,
|
|
};
|
|
|
|
static void allwinner_h3_register_types(void)
|
|
{
|
|
type_register_static(&allwinner_h3_type_info);
|
|
}
|
|
|
|
type_init(allwinner_h3_register_types)
|