Rather than relying on the X86XSaveArea structure definition, determine the offset of XSAVE state areas using CPUID leaf 0xd where possible (KVM and HVF). Signed-off-by: David Edmondson <david.edmondson@oracle.com> Message-Id: <20210705104632.2902400-8-david.edmondson@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
195 lines
5.2 KiB
C
195 lines
5.2 KiB
C
/*
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* x86 KVM CPU type initialization
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*
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* Copyright 2021 SUSE LLC
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "host-cpu.h"
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#include "kvm-cpu.h"
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#include "qapi/error.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "kvm_i386.h"
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#include "hw/core/accel-cpu.h"
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static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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/*
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* The realize order is important, since x86_cpu_realize() checks if
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* nothing else has been set by the user (or by accelerators) in
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* cpu->ucode_rev and cpu->phys_bits, and updates the CPUID results in
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* mwait.ecx.
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* This accel realization code also assumes cpu features are already expanded.
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*
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* realize order:
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*
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* x86_cpu_realize():
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* -> x86_cpu_expand_features()
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* -> cpu_exec_realizefn():
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* -> accel_cpu_realizefn()
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* kvm_cpu_realizefn() -> host_cpu_realizefn()
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* -> check/update ucode_rev, phys_bits, mwait
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*/
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if (cpu->max_features) {
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if (enable_cpu_pm && kvm_has_waitpkg()) {
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env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
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}
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if (cpu->ucode_rev == 0) {
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cpu->ucode_rev =
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kvm_arch_get_supported_msr_feature(kvm_state,
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MSR_IA32_UCODE_REV);
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}
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}
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return host_cpu_realizefn(cs, errp);
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}
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/*
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* KVM-specific features that are automatically added/removed
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* from all CPU models when KVM is enabled.
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*
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* NOTE: features can be enabled by default only if they were
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* already available in the oldest kernel version supported
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* by the KVM accelerator (see "OS requirements" section at
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* docs/system/target-i386.rst)
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*/
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static PropValue kvm_default_props[] = {
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{ "kvmclock", "on" },
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{ "kvm-nopiodelay", "on" },
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{ "kvm-asyncpf", "on" },
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{ "kvm-steal-time", "on" },
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{ "kvm-pv-eoi", "on" },
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{ "kvmclock-stable-bit", "on" },
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{ "x2apic", "on" },
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{ "kvm-msi-ext-dest-id", "off" },
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{ "acpi", "off" },
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{ "monitor", "off" },
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{ "svm", "off" },
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{ NULL, NULL },
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};
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void x86_cpu_change_kvm_default(const char *prop, const char *value)
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{
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PropValue *pv;
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for (pv = kvm_default_props; pv->prop; pv++) {
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if (!strcmp(pv->prop, prop)) {
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pv->value = value;
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break;
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}
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}
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/*
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* It is valid to call this function only for properties that
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* are already present in the kvm_default_props table.
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*/
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assert(pv->prop);
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}
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static bool lmce_supported(void)
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{
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uint64_t mce_cap = 0;
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if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
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return false;
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}
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return !!(mce_cap & MCG_LMCE_P);
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}
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static void kvm_cpu_max_instance_init(X86CPU *cpu)
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{
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CPUX86State *env = &cpu->env;
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KVMState *s = kvm_state;
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host_cpu_max_instance_init(cpu);
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if (lmce_supported()) {
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object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
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}
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env->cpuid_min_level =
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kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
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env->cpuid_min_xlevel =
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kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
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env->cpuid_min_xlevel2 =
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kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
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}
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static void kvm_cpu_xsave_init(void)
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{
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static bool first = true;
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KVMState *s = kvm_state;
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int i;
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if (!first) {
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return;
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}
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first = false;
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/* x87 and SSE states are in the legacy region of the XSAVE area. */
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x86_ext_save_areas[XSTATE_FP_BIT].offset = 0;
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x86_ext_save_areas[XSTATE_SSE_BIT].offset = 0;
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for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) {
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ExtSaveArea *esa = &x86_ext_save_areas[i];
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if (esa->size) {
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int sz = kvm_arch_get_supported_cpuid(s, 0xd, i, R_EAX);
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if (sz != 0) {
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assert(esa->size == sz);
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esa->offset = kvm_arch_get_supported_cpuid(s, 0xd, i, R_EBX);
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}
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}
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}
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}
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static void kvm_cpu_instance_init(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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host_cpu_instance_init(cpu);
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if (!kvm_irqchip_in_kernel()) {
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x86_cpu_change_kvm_default("x2apic", "off");
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} else if (kvm_irqchip_is_split() && kvm_enable_x2apic()) {
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x86_cpu_change_kvm_default("kvm-msi-ext-dest-id", "on");
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}
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/* Special cases not set in the X86CPUDefinition structs: */
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x86_cpu_apply_props(cpu, kvm_default_props);
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if (cpu->max_features) {
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kvm_cpu_max_instance_init(cpu);
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}
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kvm_cpu_xsave_init();
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}
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static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data)
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{
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AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
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acc->cpu_realizefn = kvm_cpu_realizefn;
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acc->cpu_instance_init = kvm_cpu_instance_init;
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}
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static const TypeInfo kvm_cpu_accel_type_info = {
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.name = ACCEL_CPU_NAME("kvm"),
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.parent = TYPE_ACCEL_CPU,
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.class_init = kvm_cpu_accel_class_init,
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.abstract = true,
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};
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static void kvm_cpu_accel_register_types(void)
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{
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type_register_static(&kvm_cpu_accel_type_info);
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}
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type_init(kvm_cpu_accel_register_types);
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