Given that TCG is now the only consumer of X86XSaveArea, move the structure definition and associated offset declarations and checks to a TCG specific header. Signed-off-by: David Edmondson <david.edmondson@oracle.com> Message-Id: <20210705104632.2902400-9-david.edmondson@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
82 lines
3.2 KiB
C
82 lines
3.2 KiB
C
/*
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* i386 TCG cpu class initialization functions
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TCG_CPU_H
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#define TCG_CPU_H
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#define XSAVE_FCW_FSW_OFFSET 0x000
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#define XSAVE_FTW_FOP_OFFSET 0x004
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#define XSAVE_CWD_RIP_OFFSET 0x008
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#define XSAVE_CWD_RDP_OFFSET 0x010
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#define XSAVE_MXCSR_OFFSET 0x018
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#define XSAVE_ST_SPACE_OFFSET 0x020
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#define XSAVE_XMM_SPACE_OFFSET 0x0a0
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#define XSAVE_XSTATE_BV_OFFSET 0x200
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#define XSAVE_AVX_OFFSET 0x240
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#define XSAVE_BNDREG_OFFSET 0x3c0
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#define XSAVE_BNDCSR_OFFSET 0x400
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#define XSAVE_OPMASK_OFFSET 0x440
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#define XSAVE_ZMM_HI256_OFFSET 0x480
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#define XSAVE_HI16_ZMM_OFFSET 0x680
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#define XSAVE_PKRU_OFFSET 0xa80
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typedef struct X86XSaveArea {
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X86LegacyXSaveArea legacy;
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X86XSaveHeader header;
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/* Extended save areas: */
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/* AVX State: */
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XSaveAVX avx_state;
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/* Ensure that XSaveBNDREG is properly aligned. */
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uint8_t padding[XSAVE_BNDREG_OFFSET
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- sizeof(X86LegacyXSaveArea)
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- sizeof(X86XSaveHeader)
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- sizeof(XSaveAVX)];
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/* MPX State: */
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XSaveBNDREG bndreg_state;
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XSaveBNDCSR bndcsr_state;
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/* AVX-512 State: */
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XSaveOpmask opmask_state;
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XSaveZMM_Hi256 zmm_hi256_state;
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XSaveHi16_ZMM hi16_zmm_state;
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/* PKRU State: */
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XSavePKRU pkru_state;
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} X86XSaveArea;
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) != XSAVE_FCW_FSW_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) != XSAVE_FTW_FOP_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) != XSAVE_CWD_RIP_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) != XSAVE_CWD_RDP_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) != XSAVE_MXCSR_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) != XSAVE_ST_SPACE_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) != XSAVE_XMM_SPACE_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != XSAVE_AVX_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != XSAVE_BNDREG_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != XSAVE_BNDCSR_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != XSAVE_OPMASK_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET);
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bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
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#endif /* TCG_CPU_H */
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