We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
182 lines
5.9 KiB
C
182 lines
5.9 KiB
C
/*
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* OpenRISC MMU.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Zhizhou Zhang <etouzh@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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#include "qemu/host-utils.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/loader.h"
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#endif
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#ifndef CONFIG_USER_ONLY
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static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
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target_ulong address)
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{
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*phys_addr = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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}
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static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
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target_ulong addr, int need, bool super)
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{
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int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK;
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uint32_t imr = cpu->env.tlb.itlb[idx].mr;
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uint32_t itr = cpu->env.tlb.itlb[idx].tr;
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uint32_t dmr = cpu->env.tlb.dtlb[idx].mr;
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uint32_t dtr = cpu->env.tlb.dtlb[idx].tr;
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int right, match, valid;
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/* If the ITLB and DTLB indexes map to the same page, we want to
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load all permissions all at once. If the destination pages do
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not match, zap the one we don't need. */
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if (unlikely((itr ^ dtr) & TARGET_PAGE_MASK)) {
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if (need & PAGE_EXEC) {
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dmr = dtr = 0;
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} else {
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imr = itr = 0;
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}
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}
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/* Check if either of the entries matches the source address. */
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match = (imr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_EXEC;
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match |= (dmr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_READ | PAGE_WRITE;
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/* Check if either of the entries is valid. */
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valid = imr & 1 ? PAGE_EXEC : 0;
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valid |= dmr & 1 ? PAGE_READ | PAGE_WRITE : 0;
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valid &= match;
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/* Collect the permissions from the entries. */
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right = itr & (super ? SXE : UXE) ? PAGE_EXEC : 0;
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right |= dtr & (super ? SRE : URE) ? PAGE_READ : 0;
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right |= dtr & (super ? SWE : UWE) ? PAGE_WRITE : 0;
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right &= valid;
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/* Note that above we validated that itr and dtr match on page.
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So oring them together changes nothing without having to
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check which one we needed. We also want to store to these
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variables even on failure, as it avoids compiler warnings. */
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*phys_addr = ((itr | dtr) & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE_MASK);
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*prot = right;
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qemu_log_mask(CPU_LOG_MMU,
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"MMU lookup: need %d match %d valid %d right %d -> %s\n",
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need, match, valid, right, (need & right) ? "OK" : "FAIL");
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/* Check the collective permissions are present. */
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if (likely(need & right)) {
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return 0; /* success! */
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}
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/* Determine what kind of failure we have. */
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if (need & valid) {
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return need & PAGE_EXEC ? EXCP_IPF : EXCP_DPF;
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} else {
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return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS;
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}
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}
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#endif
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static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
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int exception)
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{
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CPUState *cs = CPU(cpu);
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cs->exception_index = exception;
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cpu->env.eear = address;
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cpu->env.lock_addr = -1;
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}
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bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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int excp = EXCP_DPF;
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#ifndef CONFIG_USER_ONLY
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int prot;
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hwaddr phys_addr;
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if (mmu_idx == MMU_NOMMU_IDX) {
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/* The mmu is disabled; lookups never fail. */
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get_phys_nommu(&phys_addr, &prot, addr);
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excp = 0;
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} else {
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bool super = mmu_idx == MMU_SUPERVISOR_IDX;
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int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC
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: access_type == MMU_DATA_STORE ? PAGE_WRITE
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: PAGE_READ);
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super);
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}
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if (likely(excp == 0)) {
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tlb_set_page(cs, addr & TARGET_PAGE_MASK,
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phys_addr & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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if (probe) {
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return false;
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}
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#endif
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raise_mmu_exception(cpu, addr, excp);
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cpu_loop_exit_restore(cs, retaddr);
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}
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#ifndef CONFIG_USER_ONLY
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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int prot, excp, sr = cpu->env.sr;
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hwaddr phys_addr;
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switch (sr & (SR_DME | SR_IME)) {
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case SR_DME | SR_IME:
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/* The mmu is definitely enabled. */
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
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PAGE_EXEC | PAGE_READ | PAGE_WRITE,
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(sr & SR_SM) != 0);
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return excp ? -1 : phys_addr;
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default:
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/* The mmu is partially enabled, and we don't really have
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a "real" access type. Begin by trying the mmu, but if
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that fails try again without. */
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excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
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PAGE_EXEC | PAGE_READ | PAGE_WRITE,
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(sr & SR_SM) != 0);
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if (!excp) {
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return phys_addr;
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}
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/* fallthru */
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case 0:
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/* The mmu is definitely disabled; lookups never fail. */
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get_phys_nommu(&phys_addr, &prot, addr);
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return phys_addr;
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}
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}
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#endif
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