c38536bc80
The PSI bridge on POWER9 is very similar to POWER8. The BAR is still set through XSCOM but the controls are now entirely done with MMIOs. More interrupts are defined and the interrupt controller interface has changed to XIVE. The POWER9 model is a first example of the usage of the notify() handler of the XiveNotifier interface, linking the PSI XiveSource to its owning device model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
122 lines
3.1 KiB
C
122 lines
3.1 KiB
C
/*
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* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
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*
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* Copyright (c) 2015-2017, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PPC_PNV_PSI_H
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#define _PPC_PNV_PSI_H
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#include "hw/sysbus.h"
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#include "hw/ppc/xics.h"
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#include "hw/ppc/xive.h"
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#define TYPE_PNV_PSI "pnv-psi"
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#define PNV_PSI(obj) \
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OBJECT_CHECK(PnvPsi, (obj), TYPE_PNV_PSI)
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#define PSIHB_XSCOM_MAX 0x20
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typedef struct PnvPsi {
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SysBusDevice parent;
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MemoryRegion regs_mr;
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uint64_t bar;
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/* FSP region not supported */
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/* MemoryRegion fsp_mr; */
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uint64_t fsp_bar;
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/* Interrupt generation */
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qemu_irq *qirqs;
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/* Registers */
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uint64_t regs[PSIHB_XSCOM_MAX];
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MemoryRegion xscom_regs;
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} PnvPsi;
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#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
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#define PNV8_PSI(obj) \
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OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI)
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typedef struct Pnv8Psi {
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PnvPsi parent;
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ICSState ics;
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} Pnv8Psi;
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#define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
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#define PNV9_PSI(obj) \
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OBJECT_CHECK(Pnv9Psi, (obj), TYPE_PNV9_PSI)
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typedef struct Pnv9Psi {
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PnvPsi parent;
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XiveSource source;
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} Pnv9Psi;
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#define PNV_PSI_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
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#define PNV_PSI_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI)
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typedef struct PnvPsiClass {
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SysBusDeviceClass parent_class;
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int chip_type;
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uint32_t xscom_pcba;
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uint32_t xscom_size;
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uint64_t bar_mask;
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void (*irq_set)(PnvPsi *psi, int, bool state);
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} PnvPsiClass;
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/* The PSI and FSP interrupts are muxed on the same IRQ number */
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typedef enum PnvPsiIrq {
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PSIHB_IRQ_PSI, /* internal use only */
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PSIHB_IRQ_FSP, /* internal use only */
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PSIHB_IRQ_OCC,
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PSIHB_IRQ_FSI,
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PSIHB_IRQ_LPC_I2C,
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PSIHB_IRQ_LOCAL_ERR,
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PSIHB_IRQ_EXTERNAL,
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} PnvPsiIrq;
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#define PSI_NUM_INTERRUPTS 6
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void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
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/* P9 PSI Interrupts */
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#define PSIHB9_IRQ_PSI 0
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#define PSIHB9_IRQ_OCC 1
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#define PSIHB9_IRQ_FSI 2
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#define PSIHB9_IRQ_LPCHC 3
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#define PSIHB9_IRQ_LOCAL_ERR 4
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#define PSIHB9_IRQ_GLOBAL_ERR 5
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#define PSIHB9_IRQ_TPM 6
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#define PSIHB9_IRQ_LPC_SIRQ0 7
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#define PSIHB9_IRQ_LPC_SIRQ1 8
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#define PSIHB9_IRQ_LPC_SIRQ2 9
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#define PSIHB9_IRQ_LPC_SIRQ3 10
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#define PSIHB9_IRQ_SBE_I2C 11
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#define PSIHB9_IRQ_DIO 12
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#define PSIHB9_IRQ_PSU 13
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#define PSIHB9_NUM_IRQS 14
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void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon);
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#endif /* _PPC_PNV_PSI_H */
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