Those blanks violate the coding conventions, see scripts/checkpatch.pl. Blanks missing after colons in the changed lines were added. This patch does not try to fix tabs, long lines and other problems in the changed lines, therefore checkpatch.pl reports many violations. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
538 lines
14 KiB
C
538 lines
14 KiB
C
/*
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* VT82C686B south bridge support
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*
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* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
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* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "vt82c686.h"
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#include "i2c.h"
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#include "smbus.h"
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#include "pci.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "mips.h"
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#include "apm.h"
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#include "acpi.h"
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#include "pm_smbus.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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typedef uint32_t pci_addr_t;
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#include "pci_host.h"
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//#define DEBUG_VT82C686B
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#ifdef DEBUG_VT82C686B
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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typedef struct SuperIOConfig
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{
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uint8_t config[0xff];
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uint8_t index;
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uint8_t data;
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} SuperIOConfig;
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typedef struct VT82C686BState {
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PCIDevice dev;
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SuperIOConfig superio_conf;
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} VT82C686BState;
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static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
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{
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int can_write;
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SuperIOConfig *superio_conf = opaque;
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DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
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if (addr == 0x3f0) {
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superio_conf->index = data & 0xff;
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} else {
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/* 0x3f1 */
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switch (superio_conf->index) {
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case 0x00 ... 0xdf:
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case 0xe4:
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case 0xe5:
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case 0xe9 ... 0xed:
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case 0xf3:
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case 0xf5:
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case 0xf7:
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case 0xf9 ... 0xfb:
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case 0xfd ... 0xff:
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can_write = 0;
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break;
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default:
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can_write = 1;
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if (can_write) {
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switch (superio_conf->index) {
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case 0xe7:
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if ((data & 0xff) != 0xfe) {
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DPRINTF("chage uart 1 base. unsupported yet\n");
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}
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break;
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case 0xe8:
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if ((data & 0xff) != 0xbe) {
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DPRINTF("chage uart 2 base. unsupported yet\n");
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}
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break;
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default:
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superio_conf->config[superio_conf->index] = data & 0xff;
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}
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}
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}
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superio_conf->config[superio_conf->index] = data & 0xff;
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}
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}
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static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
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{
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SuperIOConfig *superio_conf = opaque;
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DPRINTF("superio_ioport_readb address 0x%x\n", addr);
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return (superio_conf->config[superio_conf->index]);
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}
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static void vt82c686b_reset(void * opaque)
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{
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PCIDevice *d = opaque;
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uint8_t *pci_conf = d->config;
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VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
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pci_conf[0x59] = 0x04;
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
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pci_conf[0x5f] = 0x04;
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
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vt82c->superio_conf.config[0xe0] = 0x3c;
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vt82c->superio_conf.config[0xe2] = 0x03;
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vt82c->superio_conf.config[0xe3] = 0xfc;
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vt82c->superio_conf.config[0xe6] = 0xde;
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vt82c->superio_conf.config[0xe7] = 0xfe;
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vt82c->superio_conf.config[0xe8] = 0xbe;
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}
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
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uint32_t val, int len)
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{
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VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
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DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
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address, val, len);
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pci_default_write_config(d, address, val, len);
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if (address == 0x85) { /* enable or disable super IO configure */
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if (val & 0x2) {
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/* floppy also uses 0x3f0 and 0x3f1.
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* But we do not emulate flopy,so just set it here. */
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isa_unassign_ioport(0x3f0, 2);
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register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
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&vt686->superio_conf);
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register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
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&vt686->superio_conf);
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} else {
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isa_unassign_ioport(0x3f0, 2);
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}
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}
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}
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#define ACPI_DBG_IO_ADDR 0xb044
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typedef struct VT686PMState {
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PCIDevice dev;
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ACPIPM1EVT pm1a;
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ACPIPM1CNT pm1_cnt;
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APMState apm;
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ACPIPMTimer tmr;
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PMSMBus smb;
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uint32_t smb_io_base;
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} VT686PMState;
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typedef struct VT686AC97State {
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PCIDevice dev;
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} VT686AC97State;
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typedef struct VT686MC97State {
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PCIDevice dev;
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} VT686MC97State;
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static void pm_update_sci(VT686PMState *s)
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{
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
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sci_level = (((pmsts & s->pm1a.en) &
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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qemu_set_irq(s->dev.irq[0], sci_level);
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pmsts & ACPI_BITMASK_TIMER_STATUS));
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}
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static void pm_tmr_timer(ACPIPMTimer *tmr)
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{
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VT686PMState *s = container_of(tmr, VT686PMState, tmr);
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pm_update_sci(s);
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}
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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VT686PMState *s = opaque;
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addr &= 0x0f;
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switch (addr) {
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case 0x00:
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acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
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pm_update_sci(s);
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break;
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case 0x02:
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s->pm1a.en = val;
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pm_update_sci(s);
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break;
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case 0x04:
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acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
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break;
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default:
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break;
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}
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DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
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}
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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VT686PMState *s = opaque;
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uint32_t val;
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addr &= 0x0f;
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switch (addr) {
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case 0x00:
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val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
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break;
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case 0x02:
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val = s->pm1a.en;
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break;
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case 0x04:
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val = s->pm1_cnt.cnt;
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break;
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default:
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val = 0;
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break;
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}
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DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
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return val;
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}
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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addr &= 0x0f;
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DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
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}
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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{
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VT686PMState *s = opaque;
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uint32_t val;
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addr &= 0x0f;
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switch (addr) {
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case 0x08:
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val = acpi_pm_tmr_get(&s->tmr);
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break;
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default:
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val = 0;
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break;
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}
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DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
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return val;
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}
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static void pm_io_space_update(VT686PMState *s)
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{
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uint32_t pm_io_base;
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if (s->dev.config[0x80] & 1) {
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pm_io_base = pci_get_long(s->dev.config + 0x40);
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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}
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
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address, val, len);
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pci_default_write_config(d, address, val, len);
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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VT686PMState *s = opaque;
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pm_io_space_update(s);
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return 0;
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}
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static const VMStateDescription vmstate_acpi = {
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.name = "vt82c686b_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, VT686PMState),
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VMSTATE_UINT16(pm1a.sts, VT686PMState),
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VMSTATE_UINT16(pm1a.en, VT686PMState),
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VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState),
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VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr.timer, VT686PMState),
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VMSTATE_INT64(tmr.overflow_time, VT686PMState),
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VMSTATE_END_OF_LIST()
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}
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};
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/*
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* TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
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* just register a PCI device now, functionalities will be implemented later.
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*/
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static int vt82c686b_ac97_initfn(PCIDevice *dev)
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{
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VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
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uint8_t *pci_conf = s->dev.config;
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_PARITY);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
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PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
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return 0;
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}
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void vt82c686b_ac97_init(PCIBus *bus, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create(bus, devfn, "VT82C686B_AC97");
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qdev_init_nofail(&dev->qdev);
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}
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static PCIDeviceInfo via_ac97_info = {
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.qdev.name = "VT82C686B_AC97",
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.qdev.desc = "AC97",
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.qdev.size = sizeof(VT686AC97State),
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.init = vt82c686b_ac97_initfn,
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.vendor_id = PCI_VENDOR_ID_VIA,
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.device_id = PCI_DEVICE_ID_VIA_AC97,
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.revision = 0x50,
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.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
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};
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static void vt82c686b_ac97_register(void)
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{
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pci_qdev_register(&via_ac97_info);
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}
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device_init(vt82c686b_ac97_register);
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static int vt82c686b_mc97_initfn(PCIDevice *dev)
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{
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VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
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uint8_t *pci_conf = s->dev.config;
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_VGA_PALETTE);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
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return 0;
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}
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void vt82c686b_mc97_init(PCIBus *bus, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create(bus, devfn, "VT82C686B_MC97");
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qdev_init_nofail(&dev->qdev);
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}
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static PCIDeviceInfo via_mc97_info = {
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.qdev.name = "VT82C686B_MC97",
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.qdev.desc = "MC97",
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.qdev.size = sizeof(VT686MC97State),
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.init = vt82c686b_mc97_initfn,
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.vendor_id = PCI_VENDOR_ID_VIA,
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.device_id = PCI_DEVICE_ID_VIA_MC97,
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.class_id = PCI_CLASS_COMMUNICATION_OTHER,
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.revision = 0x30,
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};
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static void vt82c686b_mc97_register(void)
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{
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pci_qdev_register(&via_mc97_info);
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}
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device_init(vt82c686b_mc97_register);
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/* vt82c686 pm init */
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static int vt82c686b_pm_initfn(PCIDevice *dev)
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{
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VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
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uint8_t *pci_conf;
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pci_conf = s->dev.config;
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pci_set_word(pci_conf + PCI_COMMAND, 0);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MEDIUM);
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/* 0x48-0x4B is Power Management I/O Base */
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pci_set_long(pci_conf + 0x48, 0x00000001);
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/* SMB ports:0xeee0~0xeeef */
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s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
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pci_conf[0x90] = s->smb_io_base | 1;
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pci_conf[0x91] = s->smb_io_base >> 8;
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pci_conf[0xd2] = 0x90;
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register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
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register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
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apm_init(&s->apm, NULL, s);
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acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
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acpi_pm1_cnt_init(&s->pm1_cnt, NULL);
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pm_smbus_init(&s->dev.qdev, &s->smb);
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return 0;
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}
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i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq)
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{
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PCIDevice *dev;
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VT686PMState *s;
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dev = pci_create(bus, devfn, "VT82C686B_PM");
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qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
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s = DO_UPCAST(VT686PMState, dev, dev);
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qdev_init_nofail(&dev->qdev);
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return s->smb.smbus;
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}
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static PCIDeviceInfo via_pm_info = {
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.qdev.name = "VT82C686B_PM",
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.qdev.desc = "PM",
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.qdev.size = sizeof(VT686PMState),
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.qdev.vmsd = &vmstate_acpi,
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.init = vt82c686b_pm_initfn,
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.config_write = pm_write_config,
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.vendor_id = PCI_VENDOR_ID_VIA,
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.device_id = PCI_DEVICE_ID_VIA_ACPI,
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.class_id = PCI_CLASS_BRIDGE_OTHER,
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.revision = 0x40,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
}
|
|
};
|
|
|
|
static void vt82c686b_pm_register(void)
|
|
{
|
|
pci_qdev_register(&via_pm_info);
|
|
}
|
|
|
|
device_init(vt82c686b_pm_register);
|
|
|
|
static const VMStateDescription vmstate_via = {
|
|
.name = "vt82c686b",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_PCI_DEVICE(dev, VT82C686BState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
/* init the PCI-to-ISA bridge */
|
|
static int vt82c686b_initfn(PCIDevice *d)
|
|
{
|
|
uint8_t *pci_conf;
|
|
uint8_t *wmask;
|
|
int i;
|
|
|
|
isa_bus_new(&d->qdev);
|
|
|
|
pci_conf = d->config;
|
|
pci_config_set_prog_interface(pci_conf, 0x0);
|
|
|
|
wmask = d->wmask;
|
|
for (i = 0x00; i < 0xff; i++) {
|
|
if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
|
|
wmask[i] = 0x00;
|
|
}
|
|
}
|
|
|
|
qemu_register_reset(vt82c686b_reset, d);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int vt82c686b_init(PCIBus *bus, int devfn)
|
|
{
|
|
PCIDevice *d;
|
|
|
|
d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
|
|
|
|
return d->devfn;
|
|
}
|
|
|
|
static PCIDeviceInfo via_info = {
|
|
.qdev.name = "VT82C686B",
|
|
.qdev.desc = "ISA bridge",
|
|
.qdev.size = sizeof(VT82C686BState),
|
|
.qdev.vmsd = &vmstate_via,
|
|
.qdev.no_user = 1,
|
|
.init = vt82c686b_initfn,
|
|
.config_write = vt82c686b_write_config,
|
|
.vendor_id = PCI_VENDOR_ID_VIA,
|
|
.device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE,
|
|
.class_id = PCI_CLASS_BRIDGE_ISA,
|
|
.revision = 0x40,
|
|
};
|
|
|
|
static void vt82c686b_register(void)
|
|
{
|
|
pci_qdev_register(&via_info);
|
|
}
|
|
device_init(vt82c686b_register);
|