qemu-patch-raspberry4/target/riscv
Michael Clark c3b03e5800 RISC-V: Improve page table walker spec compliance
- Inline PTE_TABLE check for better readability
- Change access checks from ternary operator to if
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ protection for PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-04 13:19:23 -07:00
..
cpu.c target/riscv: Honor CPU_DUMP_FPU 2018-05-18 14:52:38 -07:00
cpu.h RISC-V: Update address bits to support sv39 and sv48 2018-09-04 13:19:12 -07:00
cpu_bits.h RISC-V: Improve page table walker spec compliance 2018-09-04 13:19:23 -07:00
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
fpu_helper.c target/riscv: Remove floatX_maybe_silence_nan from conversions 2018-05-17 15:27:15 -07:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.c RISC-V: Improve page table walker spec compliance 2018-09-04 13:19:23 -07:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V: Add trailing '\n' to qemu_log() calls 2018-06-08 13:15:33 +01:00
pmp.c RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00