qemu-patch-raspberry4/target/openrisc
Stafford Horne c56e3b8670 target/openrisc: Fix exception handling status registers
I am working on testing instruction emulation patches for the linux
kernel. During testing I found these 2 issues:

 - sets DSX (delay slot exception) but never clears it
 - EEAR for illegal insns should point to the bad exception (as per
   openrisc spec) but its not

This patch fixes these two issues by clearing the DSX flag when not in a
delay slot and by setting EEAR to exception PC when handling illegal
instruction exceptions.

After this patch the openrisc kernel with latest patches boots great on
qemu and instruction emulation works.

Cc: qemu-trivial@nongnu.org
Cc: openrisc@lists.librecores.org
Signed-off-by: Stafford Horne <shorne@gmail.com>
Message-Id: <20170113220028.29687-1-shorne@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14 08:14:59 +11:00
..
cpu.c qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
cpu.h target/openrisc: Rename the cpu from or32 to or1k 2017-02-14 08:14:58 +11:00
exception.c
exception.h
exception_helper.c
fpu_helper.c
gdbstub.c
helper.h target-openrisc: Use clz and ctz opcodes 2017-01-10 08:06:11 -08:00
int_helper.c target-openrisc: Use clz and ctz opcodes 2017-01-10 08:06:11 -08:00
interrupt.c target/openrisc: Fix exception handling status registers 2017-02-14 08:14:59 +11:00
interrupt_helper.c cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
machine.c
Makefile.objs
mmu.c
mmu_helper.c
sys_helper.c cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
translate.c target-openrisc: Use clz and ctz opcodes 2017-01-10 08:06:11 -08:00