The ADC is part of NPCM7XX Module. Its behavior is controled by the ADC_CON register. It converts one of the eight analog inputs into a digital input and stores it in the ADC_DATA register when enabled. Users can alter input value by using qom-set QMP command. Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-4-wuhaotsh@google.com [PMM: Added missing hw/adc/trace.h file] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
302 lines
8.3 KiB
C
302 lines
8.3 KiB
C
/*
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* Nuvoton NPCM7xx ADC Module
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/adc/npcm7xx_adc.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "hw/registerfields.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "qemu/units.h"
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#include "trace.h"
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REG32(NPCM7XX_ADC_CON, 0x0)
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REG32(NPCM7XX_ADC_DATA, 0x4)
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/* Register field definitions. */
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#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
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#define NPCM7XX_ADC_CON_INT_EN BIT(21)
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#define NPCM7XX_ADC_CON_REFSEL BIT(19)
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#define NPCM7XX_ADC_CON_INT BIT(18)
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#define NPCM7XX_ADC_CON_EN BIT(17)
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#define NPCM7XX_ADC_CON_RST BIT(16)
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#define NPCM7XX_ADC_CON_CONV BIT(14)
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#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
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#define NPCM7XX_ADC_MAX_RESULT 1023
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#define NPCM7XX_ADC_DEFAULT_IREF 2000000
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#define NPCM7XX_ADC_CONV_CYCLES 20
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#define NPCM7XX_ADC_RESET_CYCLES 10
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#define NPCM7XX_ADC_R0_INPUT 500000
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#define NPCM7XX_ADC_R1_INPUT 1500000
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static void npcm7xx_adc_reset(NPCM7xxADCState *s)
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{
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timer_del(&s->conv_timer);
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s->con = 0x000c0001;
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s->data = 0x00000000;
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}
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static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
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{
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uint32_t result;
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result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
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if (result > NPCM7XX_ADC_MAX_RESULT) {
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result = NPCM7XX_ADC_MAX_RESULT;
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}
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return result;
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}
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static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
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{
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return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
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}
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static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
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uint32_t cycles, uint32_t prescaler)
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{
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int64_t ticks = cycles;
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int64_t ns;
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ticks *= prescaler;
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ns = clock_ticks_to_ns(clk, ticks);
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ns += now;
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timer_mod(timer, ns);
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}
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static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
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{
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uint32_t prescaler = npcm7xx_adc_prescaler(s);
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npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
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prescaler);
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}
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static void npcm7xx_adc_convert_done(void *opaque)
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{
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NPCM7xxADCState *s = opaque;
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uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
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uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
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? s->iref : s->vref;
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if (input >= NPCM7XX_ADC_NUM_INPUTS) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
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__func__, input);
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return;
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}
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s->data = npcm7xx_adc_convert(s->adci[input], ref);
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if (s->con & NPCM7XX_ADC_CON_INT_EN) {
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s->con |= NPCM7XX_ADC_CON_INT;
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qemu_irq_raise(s->irq);
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}
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s->con &= ~NPCM7XX_ADC_CON_CONV;
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}
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static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
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{
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adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
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adc->iref);
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adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
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adc->iref);
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}
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static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
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{
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uint32_t old_con = s->con;
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/* Write ADC_INT to 1 to clear it */
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if (new_con & NPCM7XX_ADC_CON_INT) {
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new_con &= ~NPCM7XX_ADC_CON_INT;
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qemu_irq_lower(s->irq);
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} else if (old_con & NPCM7XX_ADC_CON_INT) {
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new_con |= NPCM7XX_ADC_CON_INT;
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}
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s->con = new_con;
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if (s->con & NPCM7XX_ADC_CON_RST) {
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npcm7xx_adc_reset(s);
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return;
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}
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if ((s->con & NPCM7XX_ADC_CON_EN)) {
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if (s->con & NPCM7XX_ADC_CON_CONV) {
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if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
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npcm7xx_adc_start_convert(s);
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}
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} else {
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timer_del(&s->conv_timer);
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}
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}
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}
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static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint64_t value = 0;
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NPCM7xxADCState *s = opaque;
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switch (offset) {
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case A_NPCM7XX_ADC_CON:
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value = s->con;
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break;
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case A_NPCM7XX_ADC_DATA:
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value = s->data;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
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return value;
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}
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static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
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unsigned size)
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{
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NPCM7xxADCState *s = opaque;
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trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
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switch (offset) {
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case A_NPCM7XX_ADC_CON:
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npcm7xx_adc_write_con(s, v);
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break;
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case A_NPCM7XX_ADC_DATA:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
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__func__, offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid offset 0x%04" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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}
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static const struct MemoryRegionOps npcm7xx_adc_ops = {
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.read = npcm7xx_adc_read,
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.write = npcm7xx_adc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
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{
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NPCM7xxADCState *s = NPCM7XX_ADC(obj);
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npcm7xx_adc_reset(s);
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}
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static void npcm7xx_adc_hold_reset(Object *obj)
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{
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NPCM7xxADCState *s = NPCM7XX_ADC(obj);
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qemu_irq_lower(s->irq);
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}
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static void npcm7xx_adc_init(Object *obj)
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{
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NPCM7xxADCState *s = NPCM7XX_ADC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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int i;
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sysbus_init_irq(sbd, &s->irq);
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timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
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npcm7xx_adc_convert_done, s);
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memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
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TYPE_NPCM7XX_ADC, 4 * KiB);
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sysbus_init_mmio(sbd, &s->iomem);
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s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
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for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
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object_property_add_uint32_ptr(obj, "adci[*]",
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&s->adci[i], OBJ_PROP_FLAG_WRITE);
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}
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object_property_add_uint32_ptr(obj, "vref",
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&s->vref, OBJ_PROP_FLAG_WRITE);
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npcm7xx_adc_calibrate(s);
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}
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static const VMStateDescription vmstate_npcm7xx_adc = {
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.name = "npcm7xx-adc",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
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VMSTATE_UINT32(con, NPCM7xxADCState),
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VMSTATE_UINT32(data, NPCM7xxADCState),
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VMSTATE_CLOCK(clock, NPCM7xxADCState),
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VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
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VMSTATE_UINT32(vref, NPCM7xxADCState),
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VMSTATE_UINT32(iref, NPCM7xxADCState),
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VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
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NPCM7XX_ADC_NUM_CALIB),
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VMSTATE_END_OF_LIST(),
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},
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};
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static Property npcm7xx_timer_properties[] = {
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DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "NPCM7xx ADC Module";
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dc->vmsd = &vmstate_npcm7xx_adc;
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rc->phases.enter = npcm7xx_adc_enter_reset;
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rc->phases.hold = npcm7xx_adc_hold_reset;
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device_class_set_props(dc, npcm7xx_timer_properties);
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}
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static const TypeInfo npcm7xx_adc_info = {
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.name = TYPE_NPCM7XX_ADC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCM7xxADCState),
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.class_init = npcm7xx_adc_class_init,
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.instance_init = npcm7xx_adc_init,
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};
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static void npcm7xx_adc_register_types(void)
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{
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type_register_static(&npcm7xx_adc_info);
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}
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type_init(npcm7xx_adc_register_types);
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