Use less confusing naming for superio config register handling related parts that makes it clearer what belongs to this part. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <4d30a2b4b771b2ad651509885daae79d7c4fe7a8.1609584216.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
383 lines
11 KiB
C
383 lines
11 KiB
C
/*
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* VT82C686B south bridge support
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*
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* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
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* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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* This code is licensed under the GNU GPL v2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "hw/isa/vt82c686.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "hw/isa/isa.h"
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#include "hw/isa/superio.h"
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#include "migration/vmstate.h"
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#include "hw/isa/apm.h"
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#include "hw/acpi/acpi.h"
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#include "hw/i2c/pm_smbus.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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typedef struct SuperIOConfig {
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uint8_t regs[0x100];
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uint8_t index;
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uint8_t data;
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} SuperIOConfig;
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struct VT82C686BISAState {
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PCIDevice dev;
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MemoryRegion superio;
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SuperIOConfig superio_cfg;
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};
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OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
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static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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SuperIOConfig *sc = opaque;
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if (addr == 0x3f0) { /* config index register */
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sc->index = data & 0xff;
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} else {
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bool can_write = true;
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/* 0x3f1, config data register */
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trace_via_superio_write(sc->index, data & 0xff);
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switch (sc->index) {
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case 0x00 ... 0xdf:
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case 0xe4:
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case 0xe5:
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case 0xe9 ... 0xed:
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case 0xf3:
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case 0xf5:
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case 0xf7:
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case 0xf9 ... 0xfb:
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case 0xfd ... 0xff:
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can_write = false;
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break;
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/* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
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default:
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break;
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}
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if (can_write) {
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sc->regs[sc->index] = data & 0xff;
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}
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}
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}
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static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
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{
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SuperIOConfig *sc = opaque;
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uint8_t val = sc->regs[sc->index];
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trace_via_superio_read(sc->index, val);
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return val;
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}
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static const MemoryRegionOps superio_cfg_ops = {
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.read = superio_cfg_read,
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.write = superio_cfg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static void vt82c686b_isa_reset(DeviceState *dev)
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{
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VT82C686BISAState *s = VT82C686B_ISA(dev);
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uint8_t *pci_conf = s->dev.config;
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
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pci_conf[0x59] = 0x04;
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
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pci_conf[0x5f] = 0x04;
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
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s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
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s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
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s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
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s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
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s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
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s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
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}
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
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uint32_t val, int len)
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{
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VT82C686BISAState *s = VT82C686B_ISA(d);
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trace_via_isa_write(addr, val, len);
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pci_default_write_config(d, addr, val, len);
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if (addr == 0x85) { /* enable or disable super IO configure */
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memory_region_set_enabled(&s->superio, val & 0x2);
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}
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}
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struct VT686PMState {
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PCIDevice dev;
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MemoryRegion io;
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ACPIREGS ar;
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APMState apm;
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PMSMBus smb;
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uint32_t smb_io_base;
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};
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OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)
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static void pm_update_sci(VT686PMState *s)
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{
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->ar);
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sci_level = (((pmsts & s->ar.pm1.evt.en) &
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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pci_set_irq(&s->dev, sci_level);
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pmsts & ACPI_BITMASK_TIMER_STATUS));
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}
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static void pm_tmr_timer(ACPIREGS *ar)
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{
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VT686PMState *s = container_of(ar, VT686PMState, ar);
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pm_update_sci(s);
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}
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static void pm_io_space_update(VT686PMState *s)
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{
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uint32_t pm_io_base;
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pm_io_base = pci_get_long(s->dev.config + 0x40);
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pm_io_base &= 0xffc0;
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memory_region_transaction_begin();
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memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
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memory_region_set_address(&s->io, pm_io_base);
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memory_region_transaction_commit();
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}
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static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
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{
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trace_via_pm_write(addr, val, len);
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pci_default_write_config(d, addr, val, len);
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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VT686PMState *s = opaque;
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pm_io_space_update(s);
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return 0;
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}
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static const VMStateDescription vmstate_acpi = {
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.name = "vt82c686b_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = vmstate_acpi_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, VT686PMState),
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VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
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VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
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VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
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VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
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VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
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VMSTATE_END_OF_LIST()
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}
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};
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/* vt82c686 pm init */
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static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
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{
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VT686PMState *s = VT82C686B_PM(dev);
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uint8_t *pci_conf;
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pci_conf = s->dev.config;
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pci_set_word(pci_conf + PCI_COMMAND, 0);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MEDIUM);
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/* 0x48-0x4B is Power Management I/O Base */
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pci_set_long(pci_conf + 0x48, 0x00000001);
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/* SMB ports:0xeee0~0xeeef */
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s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0);
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pci_conf[0x90] = s->smb_io_base | 1;
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pci_conf[0x91] = s->smb_io_base >> 8;
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pci_conf[0xd2] = 0x90;
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pm_smbus_init(DEVICE(s), &s->smb, false);
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memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
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apm_init(dev, &s->apm, NULL, s);
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memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
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memory_region_set_enabled(&s->io, false);
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memory_region_add_subregion(get_system_io(), 0, &s->io);
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acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
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}
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static Property via_pm_properties[] = {
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DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void via_pm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = vt82c686b_pm_realize;
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k->config_write = pm_write_config;
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k->vendor_id = PCI_VENDOR_ID_VIA;
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k->device_id = PCI_DEVICE_ID_VIA_ACPI;
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k->class_id = PCI_CLASS_BRIDGE_OTHER;
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k->revision = 0x40;
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dc->desc = "PM";
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dc->vmsd = &vmstate_acpi;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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device_class_set_props(dc, via_pm_properties);
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}
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static const TypeInfo via_pm_info = {
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.name = TYPE_VT82C686B_PM,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(VT686PMState),
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.class_init = via_pm_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static const VMStateDescription vmstate_via = {
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.name = "vt82c686b",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
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VMSTATE_END_OF_LIST()
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}
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};
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/* init the PCI-to-ISA bridge */
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static void vt82c686b_realize(PCIDevice *d, Error **errp)
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{
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VT82C686BISAState *s = VT82C686B_ISA(d);
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uint8_t *pci_conf;
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ISABus *isa_bus;
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uint8_t *wmask;
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int i;
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isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
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pci_address_space_io(d), errp);
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if (!isa_bus) {
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return;
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}
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pci_conf = d->config;
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pci_config_set_prog_interface(pci_conf, 0x0);
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wmask = d->wmask;
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for (i = 0x00; i < 0xff; i++) {
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if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
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wmask[i] = 0x00;
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}
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}
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memory_region_init_io(&s->superio, OBJECT(d), &superio_cfg_ops,
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&s->superio_cfg, "superio", 2);
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memory_region_set_enabled(&s->superio, false);
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/*
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* The floppy also uses 0x3f0 and 0x3f1.
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* But we do not emulate a floppy, so just set it here.
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*/
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memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
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&s->superio);
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}
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static void via_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = vt82c686b_realize;
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k->config_write = vt82c686b_write_config;
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k->vendor_id = PCI_VENDOR_ID_VIA;
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k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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k->revision = 0x40;
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dc->reset = vt82c686b_isa_reset;
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dc->desc = "ISA bridge";
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dc->vmsd = &vmstate_via;
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/*
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* Reason: part of VIA VT82C686 southbridge, needs to be wired up,
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* e.g. by mips_fuloong2e_init()
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo via_info = {
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.name = TYPE_VT82C686B_ISA,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(VT82C686BISAState),
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.class_init = via_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
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{
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ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
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sc->serial.count = 2;
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sc->parallel.count = 1;
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sc->ide.count = 0;
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sc->floppy.count = 1;
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}
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static const TypeInfo via_superio_info = {
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.name = TYPE_VT82C686B_SUPERIO,
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.parent = TYPE_ISA_SUPERIO,
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.instance_size = sizeof(ISASuperIODevice),
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.class_size = sizeof(ISASuperIOClass),
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.class_init = vt82c686b_superio_class_init,
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};
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static void vt82c686b_register_types(void)
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{
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type_register_static(&via_pm_info);
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type_register_static(&via_superio_info);
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type_register_static(&via_info);
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}
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type_init(vt82c686b_register_types)
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