There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. This patch contains all the files, whose maintainer I could not get from ‘get_maintainer.pl’ script. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023124424.20177-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Adapted exec.c and qdev-monitor.c to new location] Signed-off-by: Thomas Huth <thuth@redhat.com>
549 lines
14 KiB
C
549 lines
14 KiB
C
/*
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* QEMU model of the Milkymist programmable FPU.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://milkymist.walle.cc/socdoc/pfpu.pdf
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include <math.h>
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#include "qom/object.h"
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/* #define TRACE_EXEC */
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#ifdef TRACE_EXEC
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# define D_EXEC(x) x
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#else
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# define D_EXEC(x)
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#endif
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enum {
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R_CTL = 0,
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R_MESHBASE,
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R_HMESHLAST,
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R_VMESHLAST,
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R_CODEPAGE,
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R_VERTICES,
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R_COLLISIONS,
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R_STRAYWRITES,
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R_LASTDMA,
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R_PC,
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R_DREGBASE,
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R_CODEBASE,
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R_MAX
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};
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enum {
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CTL_START_BUSY = (1<<0),
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};
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enum {
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OP_NOP = 0,
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OP_FADD,
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OP_FSUB,
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OP_FMUL,
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OP_FABS,
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OP_F2I,
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OP_I2F,
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OP_VECTOUT,
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OP_SIN,
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OP_COS,
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OP_ABOVE,
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OP_EQUAL,
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OP_COPY,
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OP_IF,
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OP_TSIGN,
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OP_QUAKE,
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};
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enum {
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GPR_X = 0,
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GPR_Y = 1,
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GPR_FLAGS = 2,
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};
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enum {
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LATENCY_FADD = 5,
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LATENCY_FSUB = 5,
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LATENCY_FMUL = 7,
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LATENCY_FABS = 2,
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LATENCY_F2I = 2,
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LATENCY_I2F = 3,
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LATENCY_VECTOUT = 0,
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LATENCY_SIN = 4,
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LATENCY_COS = 4,
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LATENCY_ABOVE = 2,
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LATENCY_EQUAL = 2,
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LATENCY_COPY = 2,
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LATENCY_IF = 2,
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LATENCY_TSIGN = 2,
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LATENCY_QUAKE = 2,
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MAX_LATENCY = 7
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};
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#define GPR_BEGIN 0x100
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#define GPR_END 0x17f
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#define MICROCODE_BEGIN 0x200
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#define MICROCODE_END 0x3ff
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#define MICROCODE_WORDS 2048
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#define REINTERPRET_CAST(type, val) (*((type *)&(val)))
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#ifdef TRACE_EXEC
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static const char *opcode_to_str[] = {
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"NOP", "FADD", "FSUB", "FMUL", "FABS", "F2I", "I2F", "VECTOUT",
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"SIN", "COS", "ABOVE", "EQUAL", "COPY", "IF", "TSIGN", "QUAKE",
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};
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#endif
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#define TYPE_MILKYMIST_PFPU "milkymist-pfpu"
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OBJECT_DECLARE_SIMPLE_TYPE(MilkymistPFPUState, MILKYMIST_PFPU)
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struct MilkymistPFPUState {
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SysBusDevice parent_obj;
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MemoryRegion regs_region;
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Chardev *chr;
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qemu_irq irq;
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uint32_t regs[R_MAX];
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uint32_t gp_regs[128];
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uint32_t microcode[MICROCODE_WORDS];
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int output_queue_pos;
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uint32_t output_queue[MAX_LATENCY];
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};
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static inline uint32_t
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get_dma_address(uint32_t base, uint32_t x, uint32_t y)
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{
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return base + 8 * (128 * y + x);
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}
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static inline void
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output_queue_insert(MilkymistPFPUState *s, uint32_t val, int pos)
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{
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s->output_queue[(s->output_queue_pos + pos) % MAX_LATENCY] = val;
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}
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static inline uint32_t
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output_queue_remove(MilkymistPFPUState *s)
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{
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return s->output_queue[s->output_queue_pos];
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}
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static inline void
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output_queue_advance(MilkymistPFPUState *s)
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{
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s->output_queue[s->output_queue_pos] = 0;
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s->output_queue_pos = (s->output_queue_pos + 1) % MAX_LATENCY;
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}
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static int pfpu_decode_insn(MilkymistPFPUState *s)
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{
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uint32_t pc = s->regs[R_PC];
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uint32_t insn = s->microcode[pc];
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uint32_t reg_a = (insn >> 18) & 0x7f;
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uint32_t reg_b = (insn >> 11) & 0x7f;
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uint32_t op = (insn >> 7) & 0xf;
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uint32_t reg_d = insn & 0x7f;
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uint32_t r = 0;
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int latency = 0;
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switch (op) {
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case OP_NOP:
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break;
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case OP_FADD:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]);
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float t = a + b;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_FADD;
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D_EXEC(qemu_log("ADD a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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} break;
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case OP_FSUB:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]);
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float t = a - b;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_FSUB;
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D_EXEC(qemu_log("SUB a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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} break;
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case OP_FMUL:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]);
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float t = a * b;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_FMUL;
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D_EXEC(qemu_log("MUL a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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} break;
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case OP_FABS:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float t = fabsf(a);
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_FABS;
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D_EXEC(qemu_log("ABS a=%f t=%f, r=%08x\n", a, t, r));
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} break;
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case OP_F2I:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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int32_t t = a;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_F2I;
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D_EXEC(qemu_log("F2I a=%f t=%d, r=%08x\n", a, t, r));
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} break;
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case OP_I2F:
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{
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int32_t a = REINTERPRET_CAST(int32_t, s->gp_regs[reg_a]);
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float t = a;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_I2F;
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D_EXEC(qemu_log("I2F a=%08x t=%f, r=%08x\n", a, t, r));
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} break;
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case OP_VECTOUT:
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{
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uint32_t a = cpu_to_be32(s->gp_regs[reg_a]);
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uint32_t b = cpu_to_be32(s->gp_regs[reg_b]);
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hwaddr dma_ptr =
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get_dma_address(s->regs[R_MESHBASE],
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s->gp_regs[GPR_X], s->gp_regs[GPR_Y]);
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cpu_physical_memory_write(dma_ptr, &a, 4);
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cpu_physical_memory_write(dma_ptr + 4, &b, 4);
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s->regs[R_LASTDMA] = dma_ptr + 4;
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D_EXEC(qemu_log("VECTOUT a=%08x b=%08x dma=%08x\n", a, b, dma_ptr));
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trace_milkymist_pfpu_vectout(a, b, dma_ptr);
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} break;
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case OP_SIN:
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{
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int32_t a = REINTERPRET_CAST(int32_t, s->gp_regs[reg_a]);
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float t = sinf(a * (1.0f / (M_PI * 4096.0f)));
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_SIN;
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D_EXEC(qemu_log("SIN a=%d t=%f, r=%08x\n", a, t, r));
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} break;
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case OP_COS:
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{
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int32_t a = REINTERPRET_CAST(int32_t, s->gp_regs[reg_a]);
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float t = cosf(a * (1.0f / (M_PI * 4096.0f)));
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_COS;
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D_EXEC(qemu_log("COS a=%d t=%f, r=%08x\n", a, t, r));
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} break;
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case OP_ABOVE:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]);
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float t = (a > b) ? 1.0f : 0.0f;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_ABOVE;
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D_EXEC(qemu_log("ABOVE a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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} break;
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case OP_EQUAL:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]);
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float t = (a == b) ? 1.0f : 0.0f;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_EQUAL;
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D_EXEC(qemu_log("EQUAL a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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} break;
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case OP_COPY:
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{
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r = s->gp_regs[reg_a];
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latency = LATENCY_COPY;
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D_EXEC(qemu_log("COPY"));
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} break;
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case OP_IF:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]);
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uint32_t f = s->gp_regs[GPR_FLAGS];
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float t = (f != 0) ? a : b;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_IF;
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D_EXEC(qemu_log("IF f=%u a=%f b=%f t=%f, r=%08x\n", f, a, b, t, r));
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} break;
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case OP_TSIGN:
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{
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float a = REINTERPRET_CAST(float, s->gp_regs[reg_a]);
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float b = REINTERPRET_CAST(float, s->gp_regs[reg_b]);
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float t = (b < 0) ? -a : a;
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r = REINTERPRET_CAST(uint32_t, t);
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latency = LATENCY_TSIGN;
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D_EXEC(qemu_log("TSIGN a=%f b=%f t=%f, r=%08x\n", a, b, t, r));
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} break;
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case OP_QUAKE:
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{
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uint32_t a = s->gp_regs[reg_a];
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r = 0x5f3759df - (a >> 1);
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latency = LATENCY_QUAKE;
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D_EXEC(qemu_log("QUAKE a=%d r=%08x\n", a, r));
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} break;
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default:
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error_report("milkymist_pfpu: unknown opcode %d", op);
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break;
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}
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if (!reg_d) {
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D_EXEC(qemu_log("%04d %8s R%03d, R%03d <L=%d, E=%04d>\n",
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s->regs[R_PC], opcode_to_str[op], reg_a, reg_b, latency,
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s->regs[R_PC] + latency));
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} else {
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D_EXEC(qemu_log("%04d %8s R%03d, R%03d <L=%d, E=%04d> -> R%03d\n",
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s->regs[R_PC], opcode_to_str[op], reg_a, reg_b, latency,
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s->regs[R_PC] + latency, reg_d));
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}
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if (op == OP_VECTOUT) {
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return 0;
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}
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/* store output for this cycle */
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if (reg_d) {
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uint32_t val = output_queue_remove(s);
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D_EXEC(qemu_log("R%03d <- 0x%08x\n", reg_d, val));
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s->gp_regs[reg_d] = val;
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}
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output_queue_advance(s);
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/* store op output */
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if (op != OP_NOP) {
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output_queue_insert(s, r, latency-1);
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}
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/* advance PC */
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s->regs[R_PC]++;
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return 1;
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};
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static void pfpu_start(MilkymistPFPUState *s)
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{
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int x, y;
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int i;
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for (y = 0; y <= s->regs[R_VMESHLAST]; y++) {
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for (x = 0; x <= s->regs[R_HMESHLAST]; x++) {
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D_EXEC(qemu_log("\nprocessing x=%d y=%d\n", x, y));
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/* set current position */
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s->gp_regs[GPR_X] = x;
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s->gp_regs[GPR_Y] = y;
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/* run microcode on this position */
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i = 0;
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while (pfpu_decode_insn(s)) {
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/* decode at most MICROCODE_WORDS instructions */
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if (++i >= MICROCODE_WORDS) {
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error_report("milkymist_pfpu: too many instructions "
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"executed in microcode. No VECTOUT?");
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break;
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}
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}
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/* reset pc for next run */
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s->regs[R_PC] = 0;
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}
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}
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s->regs[R_VERTICES] = x * y;
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trace_milkymist_pfpu_pulse_irq();
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qemu_irq_pulse(s->irq);
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}
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static inline int get_microcode_address(MilkymistPFPUState *s, uint32_t addr)
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{
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return (512 * s->regs[R_CODEPAGE]) + addr - MICROCODE_BEGIN;
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}
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static uint64_t pfpu_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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MilkymistPFPUState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_CTL:
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case R_MESHBASE:
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case R_HMESHLAST:
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case R_VMESHLAST:
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case R_CODEPAGE:
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case R_VERTICES:
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case R_COLLISIONS:
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case R_STRAYWRITES:
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case R_LASTDMA:
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case R_PC:
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case R_DREGBASE:
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case R_CODEBASE:
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r = s->regs[addr];
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break;
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case GPR_BEGIN ... GPR_END:
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r = s->gp_regs[addr - GPR_BEGIN];
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break;
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case MICROCODE_BEGIN ... MICROCODE_END:
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r = s->microcode[get_microcode_address(s, addr)];
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break;
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default:
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error_report("milkymist_pfpu: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_milkymist_pfpu_memory_read(addr << 2, r);
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return r;
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}
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static void pfpu_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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MilkymistPFPUState *s = opaque;
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trace_milkymist_pfpu_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_CTL:
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if (value & CTL_START_BUSY) {
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pfpu_start(s);
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}
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break;
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case R_MESHBASE:
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case R_HMESHLAST:
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case R_VMESHLAST:
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case R_CODEPAGE:
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case R_VERTICES:
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case R_COLLISIONS:
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case R_STRAYWRITES:
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case R_LASTDMA:
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case R_PC:
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case R_DREGBASE:
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case R_CODEBASE:
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s->regs[addr] = value;
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break;
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case GPR_BEGIN ... GPR_END:
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s->gp_regs[addr - GPR_BEGIN] = value;
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break;
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case MICROCODE_BEGIN ... MICROCODE_END:
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s->microcode[get_microcode_address(s, addr)] = value;
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break;
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default:
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error_report("milkymist_pfpu: write access to unknown register 0x"
|
|
TARGET_FMT_plx, addr << 2);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps pfpu_mmio_ops = {
|
|
.read = pfpu_read,
|
|
.write = pfpu_write,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void milkymist_pfpu_reset(DeviceState *d)
|
|
{
|
|
MilkymistPFPUState *s = MILKYMIST_PFPU(d);
|
|
int i;
|
|
|
|
for (i = 0; i < R_MAX; i++) {
|
|
s->regs[i] = 0;
|
|
}
|
|
for (i = 0; i < 128; i++) {
|
|
s->gp_regs[i] = 0;
|
|
}
|
|
for (i = 0; i < MICROCODE_WORDS; i++) {
|
|
s->microcode[i] = 0;
|
|
}
|
|
s->output_queue_pos = 0;
|
|
for (i = 0; i < MAX_LATENCY; i++) {
|
|
s->output_queue[i] = 0;
|
|
}
|
|
}
|
|
|
|
static void milkymist_pfpu_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
MilkymistPFPUState *s = MILKYMIST_PFPU(dev);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
memory_region_init_io(&s->regs_region, OBJECT(dev), &pfpu_mmio_ops, s,
|
|
"milkymist-pfpu", MICROCODE_END * 4);
|
|
sysbus_init_mmio(sbd, &s->regs_region);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_milkymist_pfpu = {
|
|
.name = "milkymist-pfpu",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32_ARRAY(regs, MilkymistPFPUState, R_MAX),
|
|
VMSTATE_UINT32_ARRAY(gp_regs, MilkymistPFPUState, 128),
|
|
VMSTATE_UINT32_ARRAY(microcode, MilkymistPFPUState, MICROCODE_WORDS),
|
|
VMSTATE_INT32(output_queue_pos, MilkymistPFPUState),
|
|
VMSTATE_UINT32_ARRAY(output_queue, MilkymistPFPUState, MAX_LATENCY),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void milkymist_pfpu_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = milkymist_pfpu_realize;
|
|
dc->reset = milkymist_pfpu_reset;
|
|
dc->vmsd = &vmstate_milkymist_pfpu;
|
|
}
|
|
|
|
static const TypeInfo milkymist_pfpu_info = {
|
|
.name = TYPE_MILKYMIST_PFPU,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(MilkymistPFPUState),
|
|
.class_init = milkymist_pfpu_class_init,
|
|
};
|
|
|
|
static void milkymist_pfpu_register_types(void)
|
|
{
|
|
type_register_static(&milkymist_pfpu_info);
|
|
}
|
|
|
|
type_init(milkymist_pfpu_register_types)
|