The CPUClass has a 'reset' method. This is a legacy from when TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()' function is kept as the API which most places use to reset a CPU; it is now a wrapper which calls device_cold_reset() and then the tracepoint function. This change should not cause CPU objects to be reset more often than they are at the moment, because: * nobody is directly calling device_cold_reset() or qdev_reset_all() on CPU objects * no CPU object is on a qbus, so they will not be reset either by somebody calling qbus_reset_all()/bus_cold_reset(), or by the main "reset sysbus and everything in the qbus tree" reset that most devices are reset by Note that this does not change the need for each machine or whatever to use qemu_register_reset() to arrange to call cpu_reset() -- that is necessary because CPU objects are not on any qbus, so they don't get reset when the qbus tree rooted at the sysbus bus is reset, and this isn't being changed here. All the changes to the files under target/ were made using the included Coccinelle script, except: (1) the deletion of the now-inaccurate and not terribly useful "CPUClass::reset" comments was done with a perl one-liner afterwards: perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c (2) this bit of the s390 change was done by hand, because the Coccinelle script is not sophisticated enough to handle the parent_reset call being inside another function: | @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) | S390CPU *cpu = S390_CPU(s); | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | CPUS390XState *env = &cpu->env; |+ DeviceState *dev = DEVICE(s); | |- scc->parent_reset(s); |+ scc->parent_reset(dev); | cpu->env.sigp_order = 0; | s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
266 lines
7 KiB
C
266 lines
7 KiB
C
/*
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* QEMU LatticeMico32 CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/qemu-print.h"
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#include "cpu.h"
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static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
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{
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LM32CPU *cpu = LM32_CPU(cs);
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cpu->env.pc = value;
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}
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static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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const char *typename = object_class_get_name(oc);
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char *name;
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name = g_strndup(typename, strlen(typename) - strlen(LM32_CPU_TYPE_SUFFIX));
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qemu_printf(" %s\n", name);
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g_free(name);
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}
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void lm32_cpu_list(void)
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{
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GSList *list;
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list = object_class_get_list_sorted(TYPE_LM32_CPU, false);
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qemu_printf("Available CPUs:\n");
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g_slist_foreach(list, lm32_cpu_list_entry, NULL);
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g_slist_free(list);
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}
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static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
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{
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CPULM32State *env = &cpu->env;
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uint32_t cfg = 0;
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if (cpu->features & LM32_FEATURE_MULTIPLY) {
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cfg |= CFG_M;
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}
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if (cpu->features & LM32_FEATURE_DIVIDE) {
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cfg |= CFG_D;
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}
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if (cpu->features & LM32_FEATURE_SHIFT) {
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cfg |= CFG_S;
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}
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if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
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cfg |= CFG_X;
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}
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if (cpu->features & LM32_FEATURE_I_CACHE) {
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cfg |= CFG_IC;
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}
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if (cpu->features & LM32_FEATURE_D_CACHE) {
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cfg |= CFG_DC;
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}
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if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
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cfg |= CFG_CC;
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}
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cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
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cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
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cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
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cfg |= (cpu->revision << CFG_REV_SHIFT);
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env->cfg = cfg;
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}
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static bool lm32_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & CPU_INTERRUPT_HARD;
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}
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static void lm32_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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LM32CPU *cpu = LM32_CPU(s);
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
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CPULM32State *env = &cpu->env;
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lcc->parent_reset(dev);
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/* reset cpu state */
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memset(env, 0, offsetof(CPULM32State, end_reset_fields));
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lm32_cpu_init_cfg_reg(cpu);
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}
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static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_mach_lm32;
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info->print_insn = print_insn_lm32;
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}
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static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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lcc->parent_realize(dev, errp);
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}
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static void lm32_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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CPULM32State *env = &cpu->env;
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cpu_set_cpustate_pointers(cpu);
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env->flags = 0;
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}
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static void lm32_basic_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_CYCLE_COUNT;
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}
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static void lm32_standard_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_CYCLE_COUNT;
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}
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static void lm32_full_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_D_CACHE
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| LM32_FEATURE_CYCLE_COUNT;
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}
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static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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typename = g_strdup_printf(LM32_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
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object_class_is_abstract(oc))) {
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oc = NULL;
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}
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return oc;
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}
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static void lm32_cpu_class_init(ObjectClass *oc, void *data)
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{
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LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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device_class_set_parent_realize(dc, lm32_cpu_realizefn,
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&lcc->parent_realize);
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device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset);
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cc->class_by_name = lm32_cpu_class_by_name;
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cc->has_work = lm32_cpu_has_work;
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cc->do_interrupt = lm32_cpu_do_interrupt;
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cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
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cc->dump_state = lm32_cpu_dump_state;
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cc->set_pc = lm32_cpu_set_pc;
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cc->gdb_read_register = lm32_cpu_gdb_read_register;
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cc->gdb_write_register = lm32_cpu_gdb_write_register;
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cc->tlb_fill = lm32_cpu_tlb_fill;
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#ifndef CONFIG_USER_ONLY
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cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
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cc->vmsd = &vmstate_lm32_cpu;
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#endif
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cc->gdb_num_core_regs = 32 + 7;
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cc->gdb_stop_before_watchpoint = true;
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cc->debug_excp_handler = lm32_debug_excp_handler;
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cc->disas_set_info = lm32_cpu_disas_set_info;
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cc->tcg_initialize = lm32_translate_init;
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}
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#define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
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{ \
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.parent = TYPE_LM32_CPU, \
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.name = LM32_CPU_TYPE_NAME(cpu_model), \
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.instance_init = initfn, \
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}
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static const TypeInfo lm32_cpus_type_infos[] = {
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{ /* base class should be registered first */
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.name = TYPE_LM32_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(LM32CPU),
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.instance_init = lm32_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(LM32CPUClass),
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.class_init = lm32_cpu_class_init,
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},
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DEFINE_LM32_CPU_TYPE("lm32-basic", lm32_basic_cpu_initfn),
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DEFINE_LM32_CPU_TYPE("lm32-standard", lm32_standard_cpu_initfn),
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DEFINE_LM32_CPU_TYPE("lm32-full", lm32_full_cpu_initfn),
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};
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DEFINE_TYPES(lm32_cpus_type_infos)
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