Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
520 lines
14 KiB
C
520 lines
14 KiB
C
#include "sysemu.h"
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#include "cpu.h"
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#include "qemu-char.h"
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#include "sysemu.h"
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#include "qemu-char.h"
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#include "exec.h"
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#include "helper_regs.h"
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#include "hw/spapr.h"
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#define HPTES_PER_GROUP 8
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#define HPTE_V_SSIZE_SHIFT 62
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#define HPTE_V_AVPN_SHIFT 7
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#define HPTE_V_AVPN 0x3fffffffffffff80ULL
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
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#define HPTE_V_BOLTED 0x0000000000000010ULL
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#define HPTE_V_LOCK 0x0000000000000008ULL
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#define HPTE_V_LARGE 0x0000000000000004ULL
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#define HPTE_V_SECONDARY 0x0000000000000002ULL
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#define HPTE_V_VALID 0x0000000000000001ULL
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#define HPTE_R_PP0 0x8000000000000000ULL
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#define HPTE_R_TS 0x4000000000000000ULL
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#define HPTE_R_KEY_HI 0x3000000000000000ULL
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#define HPTE_R_RPN_SHIFT 12
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#define HPTE_R_RPN 0x3ffffffffffff000ULL
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#define HPTE_R_FLAGS 0x00000000000003ffULL
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#define HPTE_R_PP 0x0000000000000003ULL
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#define HPTE_R_N 0x0000000000000004ULL
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#define HPTE_R_G 0x0000000000000008ULL
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#define HPTE_R_M 0x0000000000000010ULL
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#define HPTE_R_I 0x0000000000000020ULL
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#define HPTE_R_W 0x0000000000000040ULL
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#define HPTE_R_WIMG 0x0000000000000078ULL
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#define HPTE_R_C 0x0000000000000080ULL
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#define HPTE_R_R 0x0000000000000100ULL
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#define HPTE_R_KEY_LO 0x0000000000000e00ULL
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#define HPTE_V_1TB_SEG 0x4000000000000000ULL
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#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
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#define HPTE_V_HVLOCK 0x40ULL
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static inline int lock_hpte(void *hpte, target_ulong bits)
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{
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uint64_t pteh;
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pteh = ldq_p(hpte);
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/* We're protected by qemu's global lock here */
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if (pteh & bits) {
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return 0;
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}
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stq_p(hpte, pteh | HPTE_V_HVLOCK);
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return 1;
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}
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static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
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target_ulong pte_index)
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{
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target_ulong rb, va_low;
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rb = (v & ~0x7fULL) << 16; /* AVA field */
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va_low = pte_index >> 3;
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if (v & HPTE_V_SECONDARY) {
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va_low = ~va_low;
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}
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/* xor vsid from AVA */
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if (!(v & HPTE_V_1TB_SEG)) {
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va_low ^= v >> 12;
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} else {
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va_low ^= v >> 24;
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}
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va_low &= 0x7ff;
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if (v & HPTE_V_LARGE) {
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rb |= 1; /* L field */
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#if 0 /* Disable that P7 specific bit for now */
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if (r & 0xff000) {
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/* non-16MB large page, must be 64k */
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/* (masks depend on page size) */
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rb |= 0x1000; /* page encoding in LP field */
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rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
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rb |= (va_low & 0xfe); /* AVAL field */
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}
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#endif
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} else {
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/* 4kB page */
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rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */
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}
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rb |= (v >> 54) & 0x300; /* B field */
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return rb;
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}
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static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong pteh = args[2];
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target_ulong ptel = args[3];
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target_ulong i;
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uint8_t *hpte;
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/* only handle 4k and 16M pages for now */
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if (pteh & HPTE_V_LARGE) {
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#if 0 /* We don't support 64k pages yet */
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if ((ptel & 0xf000) == 0x1000) {
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/* 64k page */
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} else
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#endif
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if ((ptel & 0xff000) == 0) {
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/* 16M page */
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/* lowest AVA bit must be 0 for 16M pages */
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if (pteh & 0x80) {
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return H_PARAMETER;
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}
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} else {
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return H_PARAMETER;
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}
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}
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/* FIXME: bounds check the pa? */
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/* Check WIMG */
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if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
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return H_PARAMETER;
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}
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pteh &= ~0x60ULL;
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return H_PARAMETER;
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}
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7ULL;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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for (i = 0; ; ++i) {
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if (i == 8) {
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return H_PTEG_FULL;
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}
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if (((ldq_p(hpte) & HPTE_V_VALID) == 0) &&
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lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
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break;
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}
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hpte += HASH_PTE_SIZE_64;
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}
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} else {
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i = 0;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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if (!lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
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return H_PTEG_FULL;
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}
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}
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stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
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/* eieio(); FIXME: need some sort of barrier for smp? */
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stq_p(hpte, pteh);
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assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
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args[0] = pte_index + i;
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return H_SUCCESS;
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}
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static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong avpn = args[2];
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uint8_t *hpte;
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target_ulong v, r, rb;
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return H_PARAMETER;
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}
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
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/* We have no real concurrency in qemu soft-emulation, so we
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* will never actually have a contested lock */
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assert(0);
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}
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v = ldq_p(hpte);
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r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
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if ((v & HPTE_V_VALID) == 0 ||
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
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((flags & H_ANDCOND) && (v & avpn) != 0)) {
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stq_p(hpte, v & ~HPTE_V_HVLOCK);
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assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
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return H_NOT_FOUND;
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}
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args[0] = v & ~HPTE_V_HVLOCK;
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args[1] = r;
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stq_p(hpte, 0);
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rb = compute_tlbie_rb(v, r, pte_index);
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ppc_tlb_invalidate_one(env, rb);
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assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
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return H_SUCCESS;
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}
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static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong avpn = args[2];
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uint8_t *hpte;
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target_ulong v, r, rb;
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return H_PARAMETER;
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}
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
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/* We have no real concurrency in qemu soft-emulation, so we
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* will never actually have a contested lock */
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assert(0);
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}
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v = ldq_p(hpte);
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r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
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if ((v & HPTE_V_VALID) == 0 ||
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
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stq_p(hpte, v & ~HPTE_V_HVLOCK);
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assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
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return H_NOT_FOUND;
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}
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r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
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HPTE_R_KEY_HI | HPTE_R_KEY_LO);
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r |= (flags << 55) & HPTE_R_PP0;
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r |= (flags << 48) & HPTE_R_KEY_HI;
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r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
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rb = compute_tlbie_rb(v, r, pte_index);
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stq_p(hpte, v & ~HPTE_V_VALID);
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ppc_tlb_invalidate_one(env, rb);
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stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
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/* Don't need a memory barrier, due to qemu's global lock */
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stq_p(hpte, v & ~HPTE_V_HVLOCK);
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assert(!(ldq_p(hpte) & HPTE_V_HVLOCK));
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return H_SUCCESS;
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}
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static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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/* FIXME: actually implement this */
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return H_HARDWARE;
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}
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#define FLAGS_REGISTER_VPA 0x0000200000000000ULL
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#define FLAGS_REGISTER_DTL 0x0000400000000000ULL
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#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL
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#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL
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#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL
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#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
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#define VPA_MIN_SIZE 640
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#define VPA_SIZE_OFFSET 0x4
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#define VPA_SHARED_PROC_OFFSET 0x9
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#define VPA_SHARED_PROC_VAL 0x2
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static target_ulong register_vpa(CPUState *env, target_ulong vpa)
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{
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uint16_t size;
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uint8_t tmp;
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if (vpa == 0) {
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hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
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return H_HARDWARE;
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}
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if (vpa % env->dcache_line_size) {
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return H_PARAMETER;
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}
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/* FIXME: bounds check the address */
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size = lduw_be_phys(vpa + 0x4);
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if (size < VPA_MIN_SIZE) {
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return H_PARAMETER;
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}
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/* VPA is not allowed to cross a page boundary */
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if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
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return H_PARAMETER;
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}
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env->vpa = vpa;
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tmp = ldub_phys(env->vpa + VPA_SHARED_PROC_OFFSET);
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tmp |= VPA_SHARED_PROC_VAL;
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stb_phys(env->vpa + VPA_SHARED_PROC_OFFSET, tmp);
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return H_SUCCESS;
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}
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static target_ulong deregister_vpa(CPUState *env, target_ulong vpa)
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{
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if (env->slb_shadow) {
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return H_RESOURCE;
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}
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if (env->dispatch_trace_log) {
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return H_RESOURCE;
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}
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env->vpa = 0;
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return H_SUCCESS;
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}
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static target_ulong register_slb_shadow(CPUState *env, target_ulong addr)
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{
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uint32_t size;
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if (addr == 0) {
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hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
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return H_HARDWARE;
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}
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size = ldl_be_phys(addr + 0x4);
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if (size < 0x8) {
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return H_PARAMETER;
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}
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if ((addr / 4096) != ((addr + size - 1) / 4096)) {
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return H_PARAMETER;
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}
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if (!env->vpa) {
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return H_RESOURCE;
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}
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env->slb_shadow = addr;
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return H_SUCCESS;
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}
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static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr)
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{
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env->slb_shadow = 0;
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return H_SUCCESS;
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}
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static target_ulong register_dtl(CPUState *env, target_ulong addr)
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{
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uint32_t size;
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if (addr == 0) {
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hcall_dprintf("Can't cope with DTL at logical 0\n");
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return H_HARDWARE;
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}
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size = ldl_be_phys(addr + 0x4);
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if (size < 48) {
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return H_PARAMETER;
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}
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if (!env->vpa) {
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return H_RESOURCE;
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}
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env->dispatch_trace_log = addr;
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env->dtl_size = size;
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return H_SUCCESS;
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}
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static target_ulong deregister_dtl(CPUState *emv, target_ulong addr)
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{
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env->dispatch_trace_log = 0;
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env->dtl_size = 0;
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return H_SUCCESS;
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}
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static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong flags = args[0];
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target_ulong procno = args[1];
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target_ulong vpa = args[2];
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target_ulong ret = H_PARAMETER;
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CPUState *tenv;
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for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
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if (tenv->cpu_index == procno) {
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break;
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}
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}
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if (!tenv) {
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return H_PARAMETER;
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}
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switch (flags) {
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case FLAGS_REGISTER_VPA:
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ret = register_vpa(tenv, vpa);
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break;
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case FLAGS_DEREGISTER_VPA:
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ret = deregister_vpa(tenv, vpa);
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break;
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case FLAGS_REGISTER_SLBSHADOW:
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ret = register_slb_shadow(tenv, vpa);
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break;
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case FLAGS_DEREGISTER_SLBSHADOW:
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ret = deregister_slb_shadow(tenv, vpa);
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break;
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case FLAGS_REGISTER_DTL:
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ret = register_dtl(tenv, vpa);
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break;
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case FLAGS_DEREGISTER_DTL:
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ret = deregister_dtl(tenv, vpa);
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break;
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}
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return ret;
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}
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static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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env->msr |= (1ULL << MSR_EE);
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hreg_compute_hflags(env);
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if (!cpu_has_work(env)) {
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env->halted = 1;
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}
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return H_SUCCESS;
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}
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static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong rtas_r3 = args[0];
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uint32_t token = ldl_be_phys(rtas_r3);
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uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
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uint32_t nret = ldl_be_phys(rtas_r3 + 8);
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return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12,
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nret, rtas_r3 + 12 + 4*nargs);
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}
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static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
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static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
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void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
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{
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spapr_hcall_fn *slot;
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if (opcode <= MAX_HCALL_OPCODE) {
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assert((opcode & 0x3) == 0);
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slot = &papr_hypercall_table[opcode / 4];
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} else {
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assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
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slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
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}
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assert(!(*slot) || (fn == *slot));
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*slot = fn;
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}
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target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
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target_ulong *args)
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{
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if (msr_pr) {
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hcall_dprintf("Hypercall made with MSR[PR]=1\n");
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return H_PRIVILEGE;
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}
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if ((opcode <= MAX_HCALL_OPCODE)
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&& ((opcode & 0x3) == 0)) {
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spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
|
|
|
|
if (fn) {
|
|
return fn(env, spapr, opcode, args);
|
|
}
|
|
} else if ((opcode >= KVMPPC_HCALL_BASE) &&
|
|
(opcode <= KVMPPC_HCALL_MAX)) {
|
|
spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
|
|
|
|
if (fn) {
|
|
return fn(env, spapr, opcode, args);
|
|
}
|
|
}
|
|
|
|
hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
|
|
return H_FUNCTION;
|
|
}
|
|
|
|
static void hypercall_init(void)
|
|
{
|
|
/* hcall-pft */
|
|
spapr_register_hypercall(H_ENTER, h_enter);
|
|
spapr_register_hypercall(H_REMOVE, h_remove);
|
|
spapr_register_hypercall(H_PROTECT, h_protect);
|
|
|
|
/* hcall-dabr */
|
|
spapr_register_hypercall(H_SET_DABR, h_set_dabr);
|
|
|
|
/* hcall-splpar */
|
|
spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
|
|
spapr_register_hypercall(H_CEDE, h_cede);
|
|
|
|
/* qemu/KVM-PPC specific hcalls */
|
|
spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
|
|
}
|
|
device_init(hypercall_init);
|