6ebbf39000
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
149 lines
3.3 KiB
C
149 lines
3.3 KiB
C
/*
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* CRIS mmu emulation.
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*
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* Copyright (c) 2007 AXIS Communications AB
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* Written by Edgar E. Iglesias.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef CONFIG_USER_ONLY
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "config.h"
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#include "cpu.h"
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#include "mmu.h"
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#include "exec-all.h"
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static int cris_mmu_enabled(uint32_t rw_gc_cfg)
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{
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return (rw_gc_cfg & 12) != 0;
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}
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static int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
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{
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return (1 << seg) & rw_mm_cfg;
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}
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static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
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{
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uint32_t base;
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int i;
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if (seg < 8)
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base = env->sregs[SFR_RW_MM_KBASE_LO];
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else
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base = env->sregs[SFR_RW_MM_KBASE_HI];
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i = seg & 7;
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base >>= i * 4;
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base &= 15;
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base <<= 28;
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return base;
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}
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/* Used by the tlb decoder. */
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#define EXTRACT_FIELD(src, start, end) \
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(((src) >> start) & ((1 << (end - start + 1)) - 1))
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static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
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CPUState *env, uint32_t vaddr,
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int rw, int usermode)
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{
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unsigned int vpage;
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unsigned int idx;
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uint32_t lo, hi;
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uint32_t vpn, pfn = 0, pid, fg, fv, fk, fw, fx;
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int i, match = 0;
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vpage = vaddr >> 13;
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idx = vpage & 31;
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vpage >>= 4;
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/* We know the index which to check on each set.
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Scan both I and D. */
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for (i = 0; i < 4; i++)
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{
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lo = env->tlbsets[0][i][idx].lo;
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hi = env->tlbsets[0][i][idx].hi;
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vpn = EXTRACT_FIELD(hi, 13, 31);
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pid = EXTRACT_FIELD(hi, 0, 7);
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if (vpn == vpage
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&& pid == env->pregs[SR_PID]) {
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match = 1;
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break;
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}
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}
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if (match) {
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pfn = EXTRACT_FIELD(lo, 13, 31);
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fg = EXTRACT_FIELD(lo, 4, 4);
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fv = EXTRACT_FIELD(lo, 3, 3);
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fk = EXTRACT_FIELD(lo, 2, 2);
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fw = EXTRACT_FIELD(lo, 1, 1);
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fx = EXTRACT_FIELD(lo, 0, 0);
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}
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printf ("%s match=%d vaddr=%x vpage=%x vpn=%x pfn=%x pid=%x %x\n",
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__func__, match,
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vaddr, vpage,
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vpn, pfn, pid, env->pregs[SR_PID]);
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res->pfn = pfn;
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return !match;
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}
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int cris_mmu_translate(struct cris_mmu_result_t *res,
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CPUState *env, uint32_t vaddr,
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int rw, int mmu_idx)
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{
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uint32_t phy = vaddr;
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int seg;
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int miss = 0;
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int is_user = mmu_idx == MMU_USER_IDX;
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if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
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res->phy = vaddr;
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return 0;
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}
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seg = vaddr >> 28;
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if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
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{
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uint32_t base;
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miss = 0;
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base = cris_mmu_translate_seg(env, seg);
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phy = base | (0x0fffffff & vaddr);
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res->phy = phy;
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}
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else
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{
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miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
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if (!miss) {
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phy &= 8191;
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phy |= (res->pfn << 13);
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res->phy = phy;
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}
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}
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// printf ("miss=%d v=%x -> p=%x\n", miss, vaddr, phy);
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return miss;
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}
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#endif
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