Whenever SSBM is reset in the command register all state information is lost. Restarting DMA means that current_addr must be reset to the base address of the PRD table. The OS is not required to change the base address register before starting a DMA operation, it can reuse the value it wrote for an earlier request. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
201 lines
6.3 KiB
C
201 lines
6.3 KiB
C
/*
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* QEMU IDE Emulation: PCI Bus support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/pc.h>
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#include <hw/pci.h>
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#include <hw/isa.h>
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#include "block.h"
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#include "block_int.h"
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#include "sysemu.h"
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#include "dma.h"
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#include <hw/ide/pci.h>
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void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, val);
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#endif
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/* Ignore writes to SSBM if it keeps the old value */
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if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
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if (!(val & BM_CMD_START)) {
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/*
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* We can't cancel Scatter Gather DMA in the middle of the
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* operation or a partial (not full) DMA transfer would reach
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* the storage so we wait for completion instead (we beahve
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* like if the DMA was completed by the time the guest trying
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* to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
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* set).
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*
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* In the future we'll be able to safely cancel the I/O if the
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* whole DMA operation will be submitted to disk with a single
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* aio operation with preadv/pwritev.
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*/
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if (bm->aiocb) {
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qemu_aio_flush();
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#ifdef DEBUG_IDE
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if (bm->aiocb)
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printf("ide_dma_cancel: aiocb still pending");
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if (bm->status & BM_STATUS_DMAING)
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printf("ide_dma_cancel: BM_STATUS_DMAING still pending");
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#endif
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}
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} else {
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bm->cur_addr = bm->addr;
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if (!(bm->status & BM_STATUS_DMAING)) {
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bm->status |= BM_STATUS_DMAING;
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/* start dma transfer if possible */
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if (bm->dma_cb)
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bm->dma_cb(bm, 0);
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}
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}
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}
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bm->cmd = val & 0x09;
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}
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static void bmdma_addr_read(IORange *ioport, uint64_t addr,
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unsigned width, uint64_t *data)
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{
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BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
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uint32_t mask = (1ULL << (width * 8)) - 1;
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*data = (bm->addr >> (addr * 8)) & mask;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)*data);
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#endif
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}
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static void bmdma_addr_write(IORange *ioport, uint64_t addr,
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unsigned width, uint64_t data)
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{
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BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
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int shift = addr * 8;
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uint32_t mask = (1ULL << (width * 8)) - 1;
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#ifdef DEBUG_IDE
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printf("%s: 0x%08x\n", __func__, (unsigned)data);
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#endif
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bm->addr &= ~(mask << shift);
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bm->addr |= ((data & mask) << shift) & ~3;
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}
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const IORangeOps bmdma_addr_ioport_ops = {
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.read = bmdma_addr_read,
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.write = bmdma_addr_write,
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};
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static bool ide_bmdma_current_needed(void *opaque)
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{
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BMDMAState *bm = opaque;
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return (bm->cur_prd_len != 0);
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}
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static const VMStateDescription vmstate_bmdma_current = {
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.name = "ide bmdma_current",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(cur_addr, BMDMAState),
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VMSTATE_UINT32(cur_prd_last, BMDMAState),
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VMSTATE_UINT32(cur_prd_addr, BMDMAState),
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VMSTATE_UINT32(cur_prd_len, BMDMAState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_bmdma = {
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.name = "ide bmdma",
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.version_id = 3,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField []) {
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VMSTATE_UINT8(cmd, BMDMAState),
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VMSTATE_UINT8(status, BMDMAState),
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VMSTATE_UINT32(addr, BMDMAState),
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VMSTATE_INT64(sector_num, BMDMAState),
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VMSTATE_UINT32(nsector, BMDMAState),
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VMSTATE_UINT8(unit, BMDMAState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (VMStateSubsection []) {
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{
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.vmsd = &vmstate_bmdma_current,
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.needed = ide_bmdma_current_needed,
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}, {
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/* empty */
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}
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}
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};
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static int ide_pci_post_load(void *opaque, int version_id)
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{
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PCIIDEState *d = opaque;
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int i;
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for(i = 0; i < 2; i++) {
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/* current versions always store 0/1, but older version
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stored bigger values. We only need last bit */
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d->bmdma[i].unit &= 1;
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}
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return 0;
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}
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const VMStateDescription vmstate_ide_pci = {
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.name = "ide",
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.version_id = 3,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.post_load = ide_pci_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, PCIIDEState),
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VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
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vmstate_bmdma, BMDMAState),
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VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
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VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
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VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
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VMSTATE_END_OF_LIST()
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}
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};
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void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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static const int bus[4] = { 0, 0, 1, 1 };
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static const int unit[4] = { 0, 1, 0, 1 };
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int i;
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for (i = 0; i < 4; i++) {
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if (hd_table[i] == NULL)
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continue;
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ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
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}
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}
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